drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h- Extension
.h- Size
- 40142 bytes
- Lines
- 356
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_11_0_8_SH_MASK_HEADER
#define _mp_11_0_8_SH_MASK_HEADER
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFLAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.