drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_offset.h- Extension
.h- Size
- 36550 bytes
- Lines
- 366
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_11_0_2_OFFSET_HEADER
#define _mp_11_0_2_OFFSET_HEADER
// addressBlock: mp_SmuMp0_SmnDec
// base address: 0x0
#define mmMP0_SMN_C2PMSG_32 0x0060
#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_33 0x0061
#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_34 0x0062
#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_35 0x0063
#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_36 0x0064
#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_37 0x0065
#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_38 0x0066
#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_39 0x0067
#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_40 0x0068
#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_41 0x0069
#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_42 0x006a
#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_43 0x006b
#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_44 0x006c
#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_45 0x006d
#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_46 0x006e
#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_47 0x006f
#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_48 0x0070
#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_49 0x0071
#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_50 0x0072
#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_51 0x0073
#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_52 0x0074
#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_53 0x0075
#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_54 0x0076
#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_55 0x0077
#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_56 0x0078
#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_57 0x0079
#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_58 0x007a
#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_59 0x007b
#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_60 0x007c
#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_61 0x007d
#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_62 0x007e
#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_63 0x007f
#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_64 0x0080
#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_65 0x0081
#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_66 0x0082
#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_67 0x0083
#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_68 0x0084
#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_69 0x0085
#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_70 0x0086
#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_71 0x0087
#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_72 0x0088
#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_73 0x0089
#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.