drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h- Extension
.h- Size
- 36859 bytes
- Lines
- 360
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_14_0_0_OFFSET_HEADER
#define _mp_14_0_0_OFFSET_HEADER
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_0 0x0240
#define regMP1_SMN_C2PMSG_0_BASE_IDX 0
#define regMP1_SMN_C2PMSG_1 0x0241
#define regMP1_SMN_C2PMSG_1_BASE_IDX 0
#define regMP1_SMN_C2PMSG_2 0x0242
#define regMP1_SMN_C2PMSG_2_BASE_IDX 0
#define regMP1_SMN_C2PMSG_3 0x0243
#define regMP1_SMN_C2PMSG_3_BASE_IDX 0
#define regMP1_SMN_C2PMSG_4 0x0244
#define regMP1_SMN_C2PMSG_4_BASE_IDX 0
#define regMP1_SMN_C2PMSG_5 0x0245
#define regMP1_SMN_C2PMSG_5_BASE_IDX 0
#define regMP1_SMN_C2PMSG_6 0x0246
#define regMP1_SMN_C2PMSG_6_BASE_IDX 0
#define regMP1_SMN_C2PMSG_7 0x0247
#define regMP1_SMN_C2PMSG_7_BASE_IDX 0
#define regMP1_SMN_C2PMSG_8 0x0248
#define regMP1_SMN_C2PMSG_8_BASE_IDX 0
#define regMP1_SMN_C2PMSG_9 0x0249
#define regMP1_SMN_C2PMSG_9_BASE_IDX 0
#define regMP1_SMN_C2PMSG_10 0x024a
#define regMP1_SMN_C2PMSG_10_BASE_IDX 0
#define regMP1_SMN_C2PMSG_11 0x024b
#define regMP1_SMN_C2PMSG_11_BASE_IDX 0
#define regMP1_SMN_C2PMSG_12 0x024c
#define regMP1_SMN_C2PMSG_12_BASE_IDX 0
#define regMP1_SMN_C2PMSG_13 0x024d
#define regMP1_SMN_C2PMSG_13_BASE_IDX 0
#define regMP1_SMN_C2PMSG_14 0x024e
#define regMP1_SMN_C2PMSG_14_BASE_IDX 0
#define regMP1_SMN_C2PMSG_15 0x024f
#define regMP1_SMN_C2PMSG_15_BASE_IDX 0
#define regMP1_SMN_C2PMSG_16 0x0250
#define regMP1_SMN_C2PMSG_16_BASE_IDX 0
#define regMP1_SMN_C2PMSG_17 0x0251
#define regMP1_SMN_C2PMSG_17_BASE_IDX 0
#define regMP1_SMN_C2PMSG_18 0x0252
#define regMP1_SMN_C2PMSG_18_BASE_IDX 0
#define regMP1_SMN_C2PMSG_19 0x0253
#define regMP1_SMN_C2PMSG_19_BASE_IDX 0
#define regMP1_SMN_C2PMSG_20 0x0254
#define regMP1_SMN_C2PMSG_20_BASE_IDX 0
#define regMP1_SMN_C2PMSG_21 0x0255
#define regMP1_SMN_C2PMSG_21_BASE_IDX 0
#define regMP1_SMN_C2PMSG_22 0x0256
#define regMP1_SMN_C2PMSG_22_BASE_IDX 0
#define regMP1_SMN_C2PMSG_23 0x0257
#define regMP1_SMN_C2PMSG_23_BASE_IDX 0
#define regMP1_SMN_C2PMSG_24 0x0258
#define regMP1_SMN_C2PMSG_24_BASE_IDX 0
#define regMP1_SMN_C2PMSG_25 0x0259
#define regMP1_SMN_C2PMSG_25_BASE_IDX 0
#define regMP1_SMN_C2PMSG_26 0x025a
#define regMP1_SMN_C2PMSG_26_BASE_IDX 0
#define regMP1_SMN_C2PMSG_27 0x025b
#define regMP1_SMN_C2PMSG_27_BASE_IDX 0
#define regMP1_SMN_C2PMSG_28 0x025c
#define regMP1_SMN_C2PMSG_28_BASE_IDX 0
#define regMP1_SMN_C2PMSG_29 0x025d
#define regMP1_SMN_C2PMSG_29_BASE_IDX 0
#define regMP1_SMN_C2PMSG_30 0x025e
#define regMP1_SMN_C2PMSG_30_BASE_IDX 0
#define regMP1_SMN_C2PMSG_31 0x025f
#define regMP1_SMN_C2PMSG_31_BASE_IDX 0
#define regMP1_SMN_C2PMSG_32 0x0260
#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
#define regMP1_SMN_C2PMSG_33 0x0261
#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
#define regMP1_SMN_C2PMSG_34 0x0262
#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
#define regMP1_SMN_C2PMSG_35 0x0263
#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
#define regMP1_SMN_C2PMSG_36 0x0264
#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
#define regMP1_SMN_C2PMSG_37 0x0265
#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
#define regMP1_SMN_C2PMSG_38 0x0266
#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
#define regMP1_SMN_C2PMSG_39 0x0267
#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
#define regMP1_SMN_C2PMSG_40 0x0268
#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
#define regMP1_SMN_C2PMSG_41 0x0269
#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
#define regMP1_SMN_C2PMSG_42 0x026aAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.