drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_sh_mask.h- Extension
.h- Size
- 44621 bytes
- Lines
- 535
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_14_0_0_SH_MASK_HEADER
#define _mp_14_0_0_SH_MASK_HEADER
// addressBlock: mp_SmuMp1Pub_CruDec
//MP1_CRU1_MP1_FIRMWARE_FLAGS
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_0
#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_1
#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_2
#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_3
#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_4
#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_5
#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_6
#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_7
#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_8
#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_9
#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_10
#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_11
#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_12
#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_13
#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_14
#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_15
#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_16
#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_17
#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_18
#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_19
#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_20
#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_21
#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_22
#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_23
#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_24
#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_25
#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFLAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.