drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_2_offset.h- Extension
.h- Size
- 47949 bytes
- Lines
- 469
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_14_0_2_OFFSET_HEADER
#define _mp_14_0_2_OFFSET_HEADER
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_0 0x0040
#define regMP1_SMN_C2PMSG_0_BASE_IDX 1
#define regMP1_SMN_C2PMSG_1 0x0041
#define regMP1_SMN_C2PMSG_1_BASE_IDX 1
#define regMP1_SMN_C2PMSG_2 0x0042
#define regMP1_SMN_C2PMSG_2_BASE_IDX 1
#define regMP1_SMN_C2PMSG_3 0x0043
#define regMP1_SMN_C2PMSG_3_BASE_IDX 1
#define regMP1_SMN_C2PMSG_4 0x0044
#define regMP1_SMN_C2PMSG_4_BASE_IDX 1
#define regMP1_SMN_C2PMSG_5 0x0045
#define regMP1_SMN_C2PMSG_5_BASE_IDX 1
#define regMP1_SMN_C2PMSG_6 0x0046
#define regMP1_SMN_C2PMSG_6_BASE_IDX 1
#define regMP1_SMN_C2PMSG_7 0x0047
#define regMP1_SMN_C2PMSG_7_BASE_IDX 1
#define regMP1_SMN_C2PMSG_8 0x0048
#define regMP1_SMN_C2PMSG_8_BASE_IDX 1
#define regMP1_SMN_C2PMSG_9 0x0049
#define regMP1_SMN_C2PMSG_9_BASE_IDX 1
#define regMP1_SMN_C2PMSG_10 0x004a
#define regMP1_SMN_C2PMSG_10_BASE_IDX 1
#define regMP1_SMN_C2PMSG_11 0x004b
#define regMP1_SMN_C2PMSG_11_BASE_IDX 1
#define regMP1_SMN_C2PMSG_12 0x004c
#define regMP1_SMN_C2PMSG_12_BASE_IDX 1
#define regMP1_SMN_C2PMSG_13 0x004d
#define regMP1_SMN_C2PMSG_13_BASE_IDX 1
#define regMP1_SMN_C2PMSG_14 0x004e
#define regMP1_SMN_C2PMSG_14_BASE_IDX 1
#define regMP1_SMN_C2PMSG_15 0x004f
#define regMP1_SMN_C2PMSG_15_BASE_IDX 1
#define regMP1_SMN_C2PMSG_16 0x0050
#define regMP1_SMN_C2PMSG_16_BASE_IDX 1
#define regMP1_SMN_C2PMSG_17 0x0051
#define regMP1_SMN_C2PMSG_17_BASE_IDX 1
#define regMP1_SMN_C2PMSG_18 0x0052
#define regMP1_SMN_C2PMSG_18_BASE_IDX 1
#define regMP1_SMN_C2PMSG_19 0x0053
#define regMP1_SMN_C2PMSG_19_BASE_IDX 1
#define regMP1_SMN_C2PMSG_20 0x0054
#define regMP1_SMN_C2PMSG_20_BASE_IDX 1
#define regMP1_SMN_C2PMSG_21 0x0055
#define regMP1_SMN_C2PMSG_21_BASE_IDX 1
#define regMP1_SMN_C2PMSG_22 0x0056
#define regMP1_SMN_C2PMSG_22_BASE_IDX 1
#define regMP1_SMN_C2PMSG_23 0x0057
#define regMP1_SMN_C2PMSG_23_BASE_IDX 1
#define regMP1_SMN_C2PMSG_24 0x0058
#define regMP1_SMN_C2PMSG_24_BASE_IDX 1
#define regMP1_SMN_C2PMSG_25 0x0059
#define regMP1_SMN_C2PMSG_25_BASE_IDX 1
#define regMP1_SMN_C2PMSG_26 0x005a
#define regMP1_SMN_C2PMSG_26_BASE_IDX 1
#define regMP1_SMN_C2PMSG_27 0x005b
#define regMP1_SMN_C2PMSG_27_BASE_IDX 1
#define regMP1_SMN_C2PMSG_28 0x005c
#define regMP1_SMN_C2PMSG_28_BASE_IDX 1
#define regMP1_SMN_C2PMSG_29 0x005d
#define regMP1_SMN_C2PMSG_29_BASE_IDX 1
#define regMP1_SMN_C2PMSG_30 0x005e
#define regMP1_SMN_C2PMSG_30_BASE_IDX 1
#define regMP1_SMN_C2PMSG_31 0x005f
#define regMP1_SMN_C2PMSG_31_BASE_IDX 1
#define regMP1_SMN_C2PMSG_32 0x0060
#define regMP1_SMN_C2PMSG_32_BASE_IDX 1
#define regMP1_SMN_C2PMSG_33 0x0061
#define regMP1_SMN_C2PMSG_33_BASE_IDX 1
#define regMP1_SMN_C2PMSG_34 0x0062
#define regMP1_SMN_C2PMSG_34_BASE_IDX 1
#define regMP1_SMN_C2PMSG_35 0x0063
#define regMP1_SMN_C2PMSG_35_BASE_IDX 1
#define regMP1_SMN_C2PMSG_36 0x0064
#define regMP1_SMN_C2PMSG_36_BASE_IDX 1
#define regMP1_SMN_C2PMSG_37 0x0065
#define regMP1_SMN_C2PMSG_37_BASE_IDX 1
#define regMP1_SMN_C2PMSG_38 0x0066
#define regMP1_SMN_C2PMSG_38_BASE_IDX 1
#define regMP1_SMN_C2PMSG_39 0x0067
#define regMP1_SMN_C2PMSG_39_BASE_IDX 1
#define regMP1_SMN_C2PMSG_40 0x0068
#define regMP1_SMN_C2PMSG_40_BASE_IDX 1
#define regMP1_SMN_C2PMSG_41 0x0069
#define regMP1_SMN_C2PMSG_41_BASE_IDX 1Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.