drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h- Extension
.h- Size
- 44824 bytes
- Lines
- 442
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mp_15_0_0_OFFSET_HEADER
#define _mp_15_0_0_OFFSET_HEADER
// addressBlock: mp_SmuMpASP_SmnDec
// base address: 0x0
#define regMPASP_SMN_C2PMSG_60 0x007c
#define regMPASP_SMN_C2PMSG_60_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_61 0x007d
#define regMPASP_SMN_C2PMSG_61_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_62 0x007e
#define regMPASP_SMN_C2PMSG_62_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_63 0x007f
#define regMPASP_SMN_C2PMSG_63_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_64 0x0080
#define regMPASP_SMN_C2PMSG_64_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_65 0x0081
#define regMPASP_SMN_C2PMSG_65_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_66 0x0082
#define regMPASP_SMN_C2PMSG_66_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_67 0x0083
#define regMPASP_SMN_C2PMSG_67_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_68 0x0084
#define regMPASP_SMN_C2PMSG_68_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_69 0x0085
#define regMPASP_SMN_C2PMSG_69_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_70 0x0086
#define regMPASP_SMN_C2PMSG_70_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_71 0x0087
#define regMPASP_SMN_C2PMSG_71_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_72 0x0088
#define regMPASP_SMN_C2PMSG_72_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_73 0x0089
#define regMPASP_SMN_C2PMSG_73_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_74 0x008a
#define regMPASP_SMN_C2PMSG_74_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_75 0x008b
#define regMPASP_SMN_C2PMSG_75_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_76 0x008c
#define regMPASP_SMN_C2PMSG_76_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_77 0x008d
#define regMPASP_SMN_C2PMSG_77_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_78 0x008e
#define regMPASP_SMN_C2PMSG_78_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_79 0x008f
#define regMPASP_SMN_C2PMSG_79_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_100 0x00a4
#define regMPASP_SMN_C2PMSG_100_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_101 0x00a5
#define regMPASP_SMN_C2PMSG_101_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_102 0x00a6
#define regMPASP_SMN_C2PMSG_102_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_103 0x00a7
#define regMPASP_SMN_C2PMSG_103_BASE_IDX 0
#define regMPASP_SMN_C2PMSG_109 0x00ad
#define regMPASP_SMN_C2PMSG_109_BASE_IDX 0
#define regMPASP_SMN_IH_CREDIT 0x0140
#define regMPASP_SMN_IH_CREDIT_BASE_IDX 0
#define regMPASP_SMN_IH_SW_INT 0x0141
#define regMPASP_SMN_IH_SW_INT_BASE_IDX 0
#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
// addressBlock: mp_SmuMpASPPub_PcruDec
// base address: 0x3800000
#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280
#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281
#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282
#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283
#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284
#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285
#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286
#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3
#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287
#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_0 0x0040
#define regMP1_SMN_C2PMSG_0_BASE_IDX 1
#define regMP1_SMN_C2PMSG_1 0x0041
#define regMP1_SMN_C2PMSG_1_BASE_IDX 1
#define regMP1_SMN_C2PMSG_2 0x0042Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.