drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h- Extension
.h- Size
- 181690 bytes
- Lines
- 1691
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbif_6_1_OFFSET_HEADER
#define _nbif_6_1_OFFSET_HEADER
// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
// base address: 0x0
#define cfgVENDOR_ID 0x0000 // duplicate
#define cfgDEVICE_ID 0x0002 // duplicate
#define cfgCOMMAND 0x0004 // duplicate
#define cfgSTATUS 0x0006 // duplicate
#define cfgREVISION_ID 0x0008 // duplicate
#define cfgPROG_INTERFACE 0x0009 // duplicate
#define cfgSUB_CLASS 0x000a // duplicate
#define cfgBASE_CLASS 0x000b // duplicate
#define cfgCACHE_LINE 0x000c // duplicate
#define cfgLATENCY 0x000d // duplicate
#define cfgHEADER 0x000e // duplicate
#define cfgBIST 0x000f // duplicate
#define cfgBASE_ADDR_1 0x0010 // duplicate
#define cfgBASE_ADDR_2 0x0014 // duplicate
#define cfgBASE_ADDR_3 0x0018 // duplicate
#define cfgBASE_ADDR_4 0x001c // duplicate
#define cfgBASE_ADDR_5 0x0020 // duplicate
#define cfgBASE_ADDR_6 0x0024 // duplicate
#define cfgADAPTER_ID 0x002c // duplicate
#define cfgROM_BASE_ADDR 0x0030 // duplicate
#define cfgCAP_PTR 0x0034 // duplicate
#define cfgINTERRUPT_LINE 0x003c // duplicate
#define cfgINTERRUPT_PIN 0x003d // duplicate
#define cfgMIN_GRANT 0x003e // duplicate
#define cfgMAX_LATENCY 0x003f // duplicate
#define cfgVENDOR_CAP_LIST 0x0048 // duplicate
#define cfgADAPTER_ID_W 0x004c // duplicate
#define cfgPMI_CAP_LIST 0x0050 // duplicate
#define cfgPMI_CAP 0x0052 // duplicate
#define cfgPMI_STATUS_CNTL 0x0054 // duplicate
#define cfgPCIE_CAP_LIST 0x0064 // duplicate
#define cfgPCIE_CAP 0x0066 // duplicate
#define cfgDEVICE_CAP 0x0068 // duplicate
#define cfgDEVICE_CNTL 0x006c // duplicate
#define cfgDEVICE_STATUS 0x006e // duplicate
#define cfgLINK_CAP 0x0070 // duplicate
#define cfgLINK_CNTL 0x0074 // duplicate
#define cfgLINK_STATUS 0x0076 // duplicate
#define cfgDEVICE_CAP2 0x0088 // duplicate
#define cfgDEVICE_CNTL2 0x008c // duplicate
#define cfgDEVICE_STATUS2 0x008e // duplicate
#define cfgLINK_CAP2 0x0090 // duplicate
#define cfgLINK_CNTL2 0x0094 // duplicate
#define cfgLINK_STATUS2 0x0096 // duplicate
#define cfgSLOT_CAP2 0x0098 // duplicate
#define cfgSLOT_CNTL2 0x009c // duplicate
#define cfgSLOT_STATUS2 0x009e // duplicate
#define cfgMSI_CAP_LIST 0x00a0 // duplicate
#define cfgMSI_MSG_CNTL 0x00a2 // duplicate
#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate
#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate
#define cfgMSI_MSG_DATA 0x00a8 // duplicate
#define cfgMSI_MSG_DATA_64 0x00ac // duplicate
#define cfgMSI_MASK 0x00ac // duplicate
#define cfgMSI_PENDING 0x00b0 // duplicate
#define cfgMSI_MASK_64 0x00b0 // duplicate
#define cfgMSI_PENDING_64 0x00b4 // duplicate
#define cfgMSIX_CAP_LIST 0x00c0 // duplicate
#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate
#define cfgMSIX_TABLE 0x00c4 // duplicate
#define cfgMSIX_PBA 0x00c8 // duplicate
#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate
#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate
#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate
#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate
#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate
#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate
#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate
#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate
#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate
#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate
#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate
#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate
#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate
#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate
#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate
#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate
#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate
#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate
#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate
#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate
#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate
#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate
#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicateAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.