drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h- Extension
.h- Size
- 985043 bytes
- Lines
- 10282
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbif_6_1_SH_MASK_HEADER
#define _nbif_6_1_SH_MASK_HEADER
// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
//VENDOR_ID
#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
//DEVICE_ID
#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
//COMMAND
#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
#define COMMAND__AD_STEPPING__SHIFT 0x7
#define COMMAND__SERR_EN__SHIFT 0x8
#define COMMAND__FAST_B2B_EN__SHIFT 0x9
#define COMMAND__INT_DIS__SHIFT 0xa
//STATUS
#define STATUS__INT_STATUS__SHIFT 0x3
#define STATUS__CAP_LIST__SHIFT 0x4
#define STATUS__PCI_66_EN__SHIFT 0x5
#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
#define STATUS__DEVSEL_TIMING__SHIFT 0x9
#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
//REVISION_ID
#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
//PROG_INTERFACE
#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
//SUB_CLASS
#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
//BASE_CLASS
#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
//CACHE_LINE
#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
//LATENCY
#define LATENCY__LATENCY_TIMER__SHIFT 0x0
//HEADER
#define HEADER__HEADER_TYPE__SHIFT 0x0
#define HEADER__DEVICE_TYPE__SHIFT 0x7
//BIST
#define BIST__BIST_COMP__SHIFT 0x0
#define BIST__BIST_STRT__SHIFT 0x6
#define BIST__BIST_CAP__SHIFT 0x7
//BASE_ADDR_1
#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
//BASE_ADDR_2
#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
//BASE_ADDR_3
#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
//BASE_ADDR_4
#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
//BASE_ADDR_5
#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
//BASE_ADDR_6
#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
//ADAPTER_ID
#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
//ROM_BASE_ADDR
#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
//CAP_PTR
#define CAP_PTR__CAP_PTR__SHIFT 0x0
//INTERRUPT_LINE
#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
//INTERRUPT_PIN
#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
//MIN_GRANT
#define MIN_GRANT__MIN_GNT__SHIFT 0x0
//MAX_LATENCY
#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
//VENDOR_CAP_LIST
#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
//ADAPTER_ID_W
#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
//PMI_CAP_LIST
#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.