drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_3_1_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_3_1_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_3_1_sh_mask.h- Extension
.h- Size
- 3429260 bytes
- Lines
- 32807
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbif_6_3_1_SH_MASK_HEADER
#define _nbif_6_3_1_SH_MASK_HEADER
// addressBlock: nbif_bif_cfg_dev0_rc_bifcfgdecp
//IRQ_BRIDGE_CNTL
#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
// addressBlock: nbif_bif_cfg_dev0_epf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
//BIF_CFG_DEV0_EPF0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
//BIF_CFG_DEV0_EPF0_COMMAND
#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7
#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8
#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa
#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L
#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L
#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L
//BIF_CFG_DEV0_EPF0_STATUS
#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3
#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4
#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5
#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L
#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L
#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L
#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
//BIF_CFG_DEV0_EPF0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.