drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h- Extension
.h- Size
- 1628028 bytes
- Lines
- 18522
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_2_3_DEFAULT_HEADER
#define _nbio_2_3_DEFAULT_HEADER
// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
#define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
#define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
#define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_bif_bx_SYSDEC
#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
#define mmPCIE_INDEX_DEFAULT 0x00000000
#define mmPCIE_DATA_DEFAULT 0x00000000
#define mmPCIE_INDEX2_DEFAULT 0x00000000
#define mmPCIE_DATA2_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
#define mmSYSHUB_INDEX_DEFAULT 0x00000000
#define mmSYSHUB_DATA_DEFAULT 0x00000000
// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
#define mmRCC_BIF_STRAP0_DEFAULT 0x00040a00
#define mmRCC_BIF_STRAP1_DEFAULT 0x00400108
#define mmRCC_BIF_STRAP2_DEFAULT 0x000a0079
#define mmRCC_BIF_STRAP3_DEFAULT 0x00000000
#define mmRCC_BIF_STRAP4_DEFAULT 0x00100010
#define mmRCC_BIF_STRAP5_DEFAULT 0x31130010
#define mmRCC_BIF_STRAP6_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20
#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479
#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009
#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849
#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000
#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02
#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000
#define mmRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310
#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000
#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000
#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000
#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.