drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h

Extension

.h

Size

2054629 bytes

Lines

22341

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _nbio_6_1_DEFAULT_HEADER
#define _nbio_6_1_DEFAULT_HEADER


// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
#define cfgPSWUSCFG0_VENDOR_ID_DEFAULT                                            0x00000000
#define cfgPSWUSCFG0_DEVICE_ID_DEFAULT                                            0x00000000
#define cfgPSWUSCFG0_COMMAND_DEFAULT                                              0x00000000
#define cfgPSWUSCFG0_STATUS_DEFAULT                                               0x00000000
#define cfgPSWUSCFG0_REVISION_ID_DEFAULT                                          0x00000000
#define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT                                       0x00000000
#define cfgPSWUSCFG0_SUB_CLASS_DEFAULT                                            0x00000000
#define cfgPSWUSCFG0_BASE_CLASS_DEFAULT                                           0x00000000
#define cfgPSWUSCFG0_CACHE_LINE_DEFAULT                                           0x00000000
#define cfgPSWUSCFG0_LATENCY_DEFAULT                                              0x00000000
#define cfgPSWUSCFG0_HEADER_DEFAULT                                               0x00000000
#define cfgPSWUSCFG0_BIST_DEFAULT                                                 0x00000000
#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_DEFAULT                               0x00000000
#define cfgPSWUSCFG0_IO_BASE_LIMIT_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_SECONDARY_STATUS_DEFAULT                                     0x00000000
#define cfgPSWUSCFG0_MEM_BASE_LIMIT_DEFAULT                                       0x00000000
#define cfgPSWUSCFG0_PREF_BASE_LIMIT_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_PREF_BASE_UPPER_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_PREF_LIMIT_UPPER_DEFAULT                                     0x00000000
#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI_DEFAULT                                     0x00000000
#define cfgPSWUSCFG0_CAP_PTR_DEFAULT                                              0x00000000
#define cfgPSWUSCFG0_INTERRUPT_LINE_DEFAULT                                       0x000000ff
#define cfgPSWUSCFG0_INTERRUPT_PIN_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL_DEFAULT                                      0x00000000
#define cfgEXT_BRIDGE_CNTL_DEFAULT                                                0x00000000
#define cfgPSWUSCFG0_VENDOR_CAP_LIST_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_ADAPTER_ID_W_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_PMI_CAP_LIST_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_PMI_CAP_DEFAULT                                              0x00000000
#define cfgPSWUSCFG0_PMI_STATUS_CNTL_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_PCIE_CAP_LIST_DEFAULT                                        0x0000a000
#define cfgPSWUSCFG0_PCIE_CAP_DEFAULT                                             0x00000002
#define cfgPSWUSCFG0_DEVICE_CAP_DEFAULT                                           0x00000000
#define cfgPSWUSCFG0_DEVICE_CNTL_DEFAULT                                          0x00002810
#define cfgPSWUSCFG0_DEVICE_STATUS_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_LINK_CAP_DEFAULT                                             0x00011c03
#define cfgPSWUSCFG0_LINK_CNTL_DEFAULT                                            0x00000000
#define cfgPSWUSCFG0_LINK_STATUS_DEFAULT                                          0x00000001
#define cfgPSWUSCFG0_DEVICE_CAP2_DEFAULT                                          0x00000000
#define cfgPSWUSCFG0_DEVICE_CNTL2_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_DEVICE_STATUS2_DEFAULT                                       0x00000000
#define cfgPSWUSCFG0_LINK_CAP2_DEFAULT                                            0x0000000e
#define cfgPSWUSCFG0_LINK_CNTL2_DEFAULT                                           0x00000003
#define cfgPSWUSCFG0_LINK_STATUS2_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_MSI_CAP_LIST_DEFAULT                                         0x0000c000
#define cfgPSWUSCFG0_MSI_MSG_CNTL_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_MSI_MSG_DATA_DEFAULT                                         0x00000000
#define cfgPSWUSCFG0_MSI_MSG_DATA_64_DEFAULT                                      0x00000000
#define cfgPSWUSCFG0_SSID_CAP_LIST_DEFAULT                                        0x0000c800
#define cfgPSWUSCFG0_SSID_CAP_DEFAULT                                             0x00000000
#define cfgMSI_MAP_CAP_LIST_DEFAULT                                               0x00000000
#define cfgMSI_MAP_CAP_DEFAULT                                                    0x00000000
#define cfgMSI_MAP_ADDR_LO_DEFAULT                                                0x00000000
#define cfgMSI_MAP_ADDR_HI_DEFAULT                                                0x00000000
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT                    0x11000000
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT                             0x00000000
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST_DEFAULT                                 0x14000000
#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL_DEFAULT                                    0x00000000
#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS_DEFAULT                                  0x00000000
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL_DEFAULT                               0x000000fe
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS_DEFAULT                             0x00000002
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL_DEFAULT                               0x00000000
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS_DEFAULT                             0x00000002
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT                     0x15000000
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT                              0x00000000
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT                              0x00000000
#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT                        0x27020000
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS_DEFAULT                               0x00000000
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK_DEFAULT                                 0x00400000
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT                             0x00440010
#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS_DEFAULT                                 0x00000000
#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK_DEFAULT                                   0x00006000
#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT                                0x00000000
#define cfgPSWUSCFG0_PCIE_HDR_LOG0_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_PCIE_HDR_LOG1_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_PCIE_HDR_LOG2_DEFAULT                                        0x00000000
#define cfgPSWUSCFG0_PCIE_HDR_LOG3_DEFAULT                                        0x00000000

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.