drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h- Extension
.h- Size
- 374628 bytes
- Lines
- 3652
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_6_1_OFFSET_HEADER
#define _nbio_6_1_OFFSET_HEADER
// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
// base address: 0x0
#define cfgPSWUSCFG0_VENDOR_ID 0x0000
#define cfgPSWUSCFG0_DEVICE_ID 0x0002
#define cfgPSWUSCFG0_COMMAND 0x0004
#define cfgPSWUSCFG0_STATUS 0x0006
#define cfgPSWUSCFG0_REVISION_ID 0x0008
#define cfgPSWUSCFG0_PROG_INTERFACE 0x0009
#define cfgPSWUSCFG0_SUB_CLASS 0x000a
#define cfgPSWUSCFG0_BASE_CLASS 0x000b
#define cfgPSWUSCFG0_CACHE_LINE 0x000c
#define cfgPSWUSCFG0_LATENCY 0x000d
#define cfgPSWUSCFG0_HEADER 0x000e
#define cfgPSWUSCFG0_BIST 0x000f
#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018
#define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c
#define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e
#define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020
#define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024
#define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028
#define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c
#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030
#define cfgPSWUSCFG0_CAP_PTR 0x0034
#define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c
#define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d
#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e
#define cfgEXT_BRIDGE_CNTL 0x0040
#define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048
#define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c
#define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050
#define cfgPSWUSCFG0_PMI_CAP 0x0052
#define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054
#define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058
#define cfgPSWUSCFG0_PCIE_CAP 0x005a
#define cfgPSWUSCFG0_DEVICE_CAP 0x005c
#define cfgPSWUSCFG0_DEVICE_CNTL 0x0060
#define cfgPSWUSCFG0_DEVICE_STATUS 0x0062
#define cfgPSWUSCFG0_LINK_CAP 0x0064
#define cfgPSWUSCFG0_LINK_CNTL 0x0068
#define cfgPSWUSCFG0_LINK_STATUS 0x006a
#define cfgPSWUSCFG0_DEVICE_CAP2 0x007c
#define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080
#define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082
#define cfgPSWUSCFG0_LINK_CAP2 0x0084
#define cfgPSWUSCFG0_LINK_CNTL2 0x0088
#define cfgPSWUSCFG0_LINK_STATUS2 0x008a
#define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0
#define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2
#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4
#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8
#define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8
#define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac
#define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0
#define cfgPSWUSCFG0_SSID_CAP 0x00c4
#define cfgMSI_MAP_CAP_LIST 0x00c8
#define cfgMSI_MAP_CAP 0x00ca
#define cfgMSI_MAP_ADDR_LO 0x00cc
#define cfgMSI_MAP_ADDR_HI 0x00d0
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108
#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c
#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110
#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114
#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118
#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c
#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124
#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130
#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158
#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c
#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160
#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164
#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168
#define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c
#define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.