drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h- Extension
.h- Size
- 1388890 bytes
- Lines
- 13150
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_6_3_2_OFFSET_HEADER
#define _nbio_6_3_2_OFFSET_HEADER
// addressBlock: nbif0_nbif0_bif_bx_SYSDEC
// base address: 0x0
#define regBIF_BX0_SYSHUB_INDEX_OVLP 0x0008
#define regBIF_BX0_SYSHUB_INDEX_OVLP_BASE_IDX 0
#define regBIF_BX0_SYSHUB_DATA_OVLP 0x0009
#define regBIF_BX0_SYSHUB_DATA_OVLP_BASE_IDX 0
#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP 0x000a
#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX 0x000c
#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0
#define regBIF_BX0_PCIE_DATA 0x000d
#define regBIF_BX0_PCIE_DATA_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX2 0x000e
#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
#define regBIF_BX0_PCIE_DATA2 0x000f
#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX_HI 0x0010
#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0
#define regBIF_BX0_PCIE_INDEX2_HI 0x0011
#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0
#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034
#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035
#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036
#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037
#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_0 0x0038
#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_1 0x0039
#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_2 0x003a
#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_3 0x003b
#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_4 0x003c
#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_5 0x003d
#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_6 0x003e
#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_7 0x003f
#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_8 0x0040
#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_9 0x0041
#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_10 0x0042
#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_11 0x0043
#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_12 0x0044
#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_13 0x0045
#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_14 0x0046
#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1
#define regBIF_BX0_BIOS_SCRATCH_15 0x0047
#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1
#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c
#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d
#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e
#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_BIF_Engine_INTR_CNTL 0x004f
#define regBIF_BX0_BIF_Engine_INTR_CNTL_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.