drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h

Extension

.h

Size

1333875 bytes

Lines

14866

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _nbio_7_0_DEFAULT_HEADER
#define _nbio_7_0_DEFAULT_HEADER


// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
#define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT                                         0x00000000
#define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT                                         0x00000000
#define cfgNB_NBCFG0_NB_COMMAND_DEFAULT                                           0x00000000
#define cfgNB_NBCFG0_NB_STATUS_DEFAULT                                            0x00000000
#define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT                                         0x00000000
#define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT                                         0x00000000
#define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_LATENCY_DEFAULT                                           0x00000000
#define cfgNB_NBCFG0_NB_HEADER_DEFAULT                                            0x00000080
#define cfgNB_NBCFG0_NB_ADAPTER_ID_DEFAULT                                        0x15d01022
#define cfgNB_NBCFG0_NB_CAPABILITIES_PTR_DEFAULT                                  0x00000000
#define cfgNB_NBCFG0_NB_HEADER_W_DEFAULT                                          0x00000080
#define cfgNB_NBCFG0_NB_PCI_CTRL_DEFAULT                                          0x00000000
#define cfgNB_NBCFG0_NB_ADAPTER_ID_W_DEFAULT                                      0x15d01022
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_0_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_0_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NBCFG_SCRATCH_0_DEFAULT                                      0x00000000
#define cfgNB_NBCFG0_NBCFG_SCRATCH_1_DEFAULT                                      0x00000000
#define cfgNB_NBCFG0_NBCFG_SCRATCH_2_DEFAULT                                      0x00000000
#define cfgNB_NBCFG0_NBCFG_SCRATCH_3_DEFAULT                                      0x00000000
#define cfgNB_NBCFG0_NBCFG_SCRATCH_4_DEFAULT                                      0x00000000
#define cfgNB_NBCFG0_NB_PCI_ARB_DEFAULT                                           0x00000108
#define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE_DEFAULT                                   0x00000000
#define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1_DEFAULT                                 0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_1_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_1_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0_DEFAULT                                 0x00000000
#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1_DEFAULT                                 0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_2_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_2_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_3_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_3_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_4_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_4_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5_DEFAULT                             0x00000000
#define cfgNB_NBCFG0_NB_SMN_INDEX_5_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_5_DEFAULT                                        0x00000000
#define cfgNB_NBCFG0_NB_PERF_CNT_CTRL_DEFAULT                                     0x00808000
#define cfgNB_NBCFG0_NB_SMN_INDEX_6_DEFAULT                                       0x00000000
#define cfgNB_NBCFG0_NB_SMN_DATA_6_DEFAULT                                        0x00000000


// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
#define cfgIOMMU_L2_0_IOMMU_VENDOR_ID_DEFAULT                                     0x00001022
#define cfgIOMMU_L2_0_IOMMU_DEVICE_ID_DEFAULT                                     0x000015d1
#define cfgIOMMU_L2_0_IOMMU_COMMAND_DEFAULT                                       0x00000000
#define cfgIOMMU_L2_0_IOMMU_STATUS_DEFAULT                                        0x00000000
#define cfgIOMMU_L2_0_IOMMU_REVISION_ID_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_REGPROG_INF_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_SUB_CLASS_DEFAULT                                     0x00000000
#define cfgIOMMU_L2_0_IOMMU_BASE_CODE_DEFAULT                                     0x00000000
#define cfgIOMMU_L2_0_IOMMU_CACHE_LINE_DEFAULT                                    0x00000000
#define cfgIOMMU_L2_0_IOMMU_LATENCY_DEFAULT                                       0x00000000
#define cfgIOMMU_L2_0_IOMMU_HEADER_DEFAULT                                        0x00000000
#define cfgIOMMU_L2_0_IOMMU_BIST_DEFAULT                                          0x00000000
#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_DEFAULT                                    0x00000000
#define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR_DEFAULT                              0x00000000
#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE_DEFAULT                                0x00000000
#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN_DEFAULT                                 0x00000001
#define cfgIOMMU_L2_0_IOMMU_CAP_HEADER_DEFAULT                                    0x00000000
#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_CAP_RANGE_DEFAULT                                     0x00000000
#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_DEFAULT                                      0x00003000
#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1_DEFAULT                                    0x00000080
#define cfgIOMMU_L2_0_IOMMU_MSI_CAP_DEFAULT                                       0x00000000
#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI_DEFAULT                                   0x00000000
#define cfgIOMMU_L2_0_IOMMU_MSI_DATA_DEFAULT                                      0x00000000
#define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP_DEFAULT                               0x00000000
#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W_DEFAULT                                  0x00000000
#define cfgIOMMU_L2_0_IOMMU_CONTROL_W_DEFAULT                                     0x00002b01
#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W_DEFAULT                               0x62201ada
#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W_DEFAULT                               0x0003cfcf
#define cfgIOMMU_L2_0_IOMMU_RANGE_W_DEFAULT                                       0x00000000
#define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL_DEFAULT                                  0x00000000
#define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0_DEFAULT                                  0x00000000
#define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0_DEFAULT                                  0x00000000

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.