drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h- Extension
.h- Size
- 495783 bytes
- Lines
- 4643
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_7_0_OFFSET_HEADER
#define _nbio_7_0_OFFSET_HEADER
// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
// base address: 0x0
#define cfgNB_NBCFG0_NB_VENDOR_ID 0x0000
#define cfgNB_NBCFG0_NB_DEVICE_ID 0x0002
#define cfgNB_NBCFG0_NB_COMMAND 0x0004
#define cfgNB_NBCFG0_NB_STATUS 0x0006
#define cfgNB_NBCFG0_NB_REVISION_ID 0x0008
#define cfgNB_NBCFG0_NB_REGPROG_INF 0x0009
#define cfgNB_NBCFG0_NB_SUB_CLASS 0x000a
#define cfgNB_NBCFG0_NB_BASE_CODE 0x000b
#define cfgNB_NBCFG0_NB_CACHE_LINE 0x000c
#define cfgNB_NBCFG0_NB_LATENCY 0x000d
#define cfgNB_NBCFG0_NB_HEADER 0x000e
#define cfgNB_NBCFG0_NB_ADAPTER_ID 0x002c
#define cfgNB_NBCFG0_NB_CAPABILITIES_PTR 0x0034
#define cfgNB_NBCFG0_NB_HEADER_W 0x0048
#define cfgNB_NBCFG0_NB_PCI_CTRL 0x004c
#define cfgNB_NBCFG0_NB_ADAPTER_ID_W 0x0050
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 0x005c
#define cfgNB_NBCFG0_NB_SMN_INDEX_0 0x0060
#define cfgNB_NBCFG0_NB_SMN_DATA_0 0x0064
#define cfgNB_NBCFG0_NBCFG_SCRATCH_0 0x0068
#define cfgNB_NBCFG0_NBCFG_SCRATCH_1 0x006c
#define cfgNB_NBCFG0_NBCFG_SCRATCH_2 0x0070
#define cfgNB_NBCFG0_NBCFG_SCRATCH_3 0x0074
#define cfgNB_NBCFG0_NBCFG_SCRATCH_4 0x0078
#define cfgNB_NBCFG0_NB_PCI_ARB 0x0084
#define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE 0x0088
#define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 0x0090
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 0x009c
#define cfgNB_NBCFG0_NB_SMN_INDEX_1 0x00a0
#define cfgNB_NBCFG0_NB_SMN_DATA_1 0x00a4
#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0 0x00a8
#define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1 0x00ac
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 0x00b4
#define cfgNB_NBCFG0_NB_SMN_INDEX_2 0x00b8
#define cfgNB_NBCFG0_NB_SMN_DATA_2 0x00bc
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 0x00c0
#define cfgNB_NBCFG0_NB_SMN_INDEX_3 0x00c4
#define cfgNB_NBCFG0_NB_SMN_DATA_3 0x00c8
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 0x00cc
#define cfgNB_NBCFG0_NB_SMN_INDEX_4 0x00d0
#define cfgNB_NBCFG0_NB_SMN_DATA_4 0x00d4
#define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 0x00dc
#define cfgNB_NBCFG0_NB_SMN_INDEX_5 0x00e0
#define cfgNB_NBCFG0_NB_SMN_DATA_5 0x00e4
#define cfgNB_NBCFG0_NB_PERF_CNT_CTRL 0x00f4
#define cfgNB_NBCFG0_NB_SMN_INDEX_6 0x00f8
#define cfgNB_NBCFG0_NB_SMN_DATA_6 0x00fc
// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
// base address: 0x0
#define cfgIOMMU_L2_0_IOMMU_VENDOR_ID 0x0000
#define cfgIOMMU_L2_0_IOMMU_DEVICE_ID 0x0002
#define cfgIOMMU_L2_0_IOMMU_COMMAND 0x0004
#define cfgIOMMU_L2_0_IOMMU_STATUS 0x0006
#define cfgIOMMU_L2_0_IOMMU_REVISION_ID 0x0008
#define cfgIOMMU_L2_0_IOMMU_REGPROG_INF 0x0009
#define cfgIOMMU_L2_0_IOMMU_SUB_CLASS 0x000a
#define cfgIOMMU_L2_0_IOMMU_BASE_CODE 0x000b
#define cfgIOMMU_L2_0_IOMMU_CACHE_LINE 0x000c
#define cfgIOMMU_L2_0_IOMMU_LATENCY 0x000d
#define cfgIOMMU_L2_0_IOMMU_HEADER 0x000e
#define cfgIOMMU_L2_0_IOMMU_BIST 0x000f
#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID 0x002c
#define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR 0x0034
#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE 0x003c
#define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN 0x003d
#define cfgIOMMU_L2_0_IOMMU_CAP_HEADER 0x0040
#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO 0x0044
#define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI 0x0048
#define cfgIOMMU_L2_0_IOMMU_CAP_RANGE 0x004c
#define cfgIOMMU_L2_0_IOMMU_CAP_MISC 0x0050
#define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1 0x0054
#define cfgIOMMU_L2_0_IOMMU_MSI_CAP 0x0064
#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO 0x0068
#define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI 0x006c
#define cfgIOMMU_L2_0_IOMMU_MSI_DATA 0x0070
#define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP 0x0074
#define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W 0x0078
#define cfgIOMMU_L2_0_IOMMU_CONTROL_W 0x007c
#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W 0x0080
#define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W 0x0084
#define cfgIOMMU_L2_0_IOMMU_RANGE_W 0x0088Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.