drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h

Extension

.h

Size

2990 bytes

Lines

64

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _nbio_7_0_SMN_HEADER
#define _nbio_7_0_SMN_HEADER


#define smnCPM_CONTROL					0x11180460
#define smnPCIE_CNTL2					0x11180070

#define smnPCIE_PERF_COUNT_CNTL				0x11180200
#define smnPCIE_PERF_CNTL_TXCLK				0x11180204
#define smnPCIE_PERF_COUNT0_TXCLK			0x11180208
#define smnPCIE_PERF_COUNT1_TXCLK			0x1118020c
#define smnPCIE_PERF_CNTL_MST_R_CLK			0x11180210
#define smnPCIE_PERF_COUNT0_MST_R_CLK			0x11180214
#define smnPCIE_PERF_COUNT1_MST_R_CLK			0x11180218
#define smnPCIE_PERF_CNTL_MST_C_CLK			0x1118021c
#define smnPCIE_PERF_COUNT0_MST_C_CLK			0x11180220
#define smnPCIE_PERF_COUNT1_MST_C_CLK			0x11180224
#define smnPCIE_PERF_CNTL_SLV_R_CLK			0x11180228
#define smnPCIE_PERF_COUNT0_SLV_R_CLK			0x1118022c
#define smnPCIE_PERF_COUNT1_SLV_R_CLK			0x11180230
#define smnPCIE_PERF_CNTL_SLV_S_C_CLK			0x11180234
#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK			0x11180238
#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK			0x1118023c
#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK			0x11180240
#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK		0x11180244
#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK		0x11180248
#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL		0x1118024c
#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL		0x11180250
#define smnPCIE_PERF_CNTL_TXCLK2			0x11180254
#define smnPCIE_PERF_COUNT0_TXCLK2			0x11180258
#define smnPCIE_PERF_COUNT1_TXCLK2			0x1118025c
#define smnPCIE_PERF_CNTL_TXCLK3                        0x1118021c
#define smnPCIE_PERF_COUNT0_TXCLK3                      0x11180220
#define smnPCIE_PERF_COUNT1_TXCLK3                      0x11180224
#define smnPCIE_PERF_CNTL_TXCLK4                        0x11180228
#define smnPCIE_PERF_COUNT0_TXCLK4                      0x1118022c
#define smnPCIE_PERF_COUNT1_TXCLK4                      0x11180230

#define smnPCIE_RX_NUM_NAK				0x11180038
#define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c

#endif	// _nbio_7_0_SMN_HEADER

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.