drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h- Extension
.h- Size
- 995588 bytes
- Lines
- 9407
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_7_11_0_OFFSET_HEADER
#define _nbio_7_11_0_OFFSET_HEADER
// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
// base address: 0x0
#define cfgNBCFG_SCRATCH_0 0x0068
#define cfgNBCFG_SCRATCH_1 0x006c
#define cfgNBCFG_SCRATCH_2 0x0070
#define cfgNBCFG_SCRATCH_3 0x0074
#define cfgNBCFG_SCRATCH_4 0x0078
// addressBlock: nbio_iohub_iommu_l2_iommul2cfg
// base address: 0x0
// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
// base address: 0x0
#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0580
// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
// base address: 0x13b00000
#define regNB_NBCFG0_NB_VENDOR_ID 0xe80000
#define regNB_NBCFG0_NB_VENDOR_ID_BASE_IDX 5
#define regNB_NBCFG0_NB_DEVICE_ID 0xe80000
#define regNB_NBCFG0_NB_DEVICE_ID_BASE_IDX 5
#define regNB_NBCFG0_NB_COMMAND 0xe80001
#define regNB_NBCFG0_NB_COMMAND_BASE_IDX 5
#define regNB_NBCFG0_NB_STATUS 0xe80001
#define regNB_NBCFG0_NB_STATUS_BASE_IDX 5
#define regNB_NBCFG0_NB_SUB_CLASS 0xe80002
#define regNB_NBCFG0_NB_SUB_CLASS_BASE_IDX 5
#define regNB_NBCFG0_NB_BASE_CODE 0xe80002
#define regNB_NBCFG0_NB_BASE_CODE_BASE_IDX 5
#define regNB_NBCFG0_NB_CACHE_LINE 0xe80003
#define regNB_NBCFG0_NB_CACHE_LINE_BASE_IDX 5
#define regNB_NBCFG0_NB_LATENCY 0xe80003
#define regNB_NBCFG0_NB_LATENCY_BASE_IDX 5
#define regNB_NBCFG0_NB_HEADER 0xe80003
#define regNB_NBCFG0_NB_HEADER_BASE_IDX 5
#define regNB_NBCFG0_NB_ADAPTER_ID 0xe8000b
#define regNB_NBCFG0_NB_ADAPTER_ID_BASE_IDX 5
#define regNB_NBCFG0_NB_CAPABILITIES_PTR 0xe8000d
#define regNB_NBCFG0_NB_CAPABILITIES_PTR_BASE_IDX 5
#define regNB_NBCFG0_NB_HEADER_W 0xe80012
#define regNB_NBCFG0_NB_HEADER_W_BASE_IDX 5
#define regNB_NBCFG0_NB_PCI_CTRL 0xe80013
#define regNB_NBCFG0_NB_PCI_CTRL_BASE_IDX 5
#define regNB_NBCFG0_NB_ADAPTER_ID_W 0xe80014
#define regNB_NBCFG0_NB_ADAPTER_ID_W_BASE_IDX 5
#define regNB_NBCFG0_NBCFG_SCRATCH_0 0xe8001a
#define regNB_NBCFG0_NBCFG_SCRATCH_0_BASE_IDX 5
#define regNB_NBCFG0_NBCFG_SCRATCH_1 0xe8001b
#define regNB_NBCFG0_NBCFG_SCRATCH_1_BASE_IDX 5
#define regNB_NBCFG0_NBCFG_SCRATCH_2 0xe8001c
#define regNB_NBCFG0_NBCFG_SCRATCH_2_BASE_IDX 5
#define regNB_NBCFG0_NBCFG_SCRATCH_3 0xe8001d
#define regNB_NBCFG0_NBCFG_SCRATCH_3_BASE_IDX 5
#define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e
#define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 5
#define regNB_NBCFG0_NB_PCI_ARB 0xe80021
#define regNB_NBCFG0_NB_PCI_ARB_BASE_IDX 5
#define regNB_NBCFG0_NB_DRAM_SLOT1_BASE 0xe80022
#define regNB_NBCFG0_NB_DRAM_SLOT1_BASE_BASE_IDX 5
#define regNB_NBCFG0_NB_INDEX_DATA_MUTEX0 0xe8002a
#define regNB_NBCFG0_NB_INDEX_DATA_MUTEX0_BASE_IDX 5
#define regNB_NBCFG0_NB_INDEX_DATA_MUTEX1 0xe8002b
#define regNB_NBCFG0_NB_INDEX_DATA_MUTEX1_BASE_IDX 5
#define regNB_NBCFG0_NB_VENDOR_ID_W 0xe80040
#define regNB_NBCFG0_NB_VENDOR_ID_W_BASE_IDX 5
#define regNB_NBCFG0_NB_DEVICE_ID_W 0xe80040
#define regNB_NBCFG0_NB_DEVICE_ID_W_BASE_IDX 5
// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
// base address: 0x13b07000
#define regFASTREG_APERTURE 0xe81c00
#define regFASTREG_APERTURE_BASE_IDX 5
// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
// base address: 0x13b10000
#define regNB_CNTL 0xe84000
#define regNB_CNTL_BASE_IDX 5
#define regNB_SPARE1 0xe84003
#define regNB_SPARE1_BASE_IDX 5
#define regNB_SPARE2 0xe84004Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.