drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h- Extension
.h- Size
- 6165450 bytes
- Lines
- 57900
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _nbio_7_11_0_SH_MASK_HEADER
#define _nbio_7_11_0_SH_MASK_HEADER
// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
//NB_VENDOR_ID
#define NB_VENDOR_ID__VENDOR_ID__SHIFT 0x0
#define NB_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
//NB_DEVICE_ID
#define NB_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define NB_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
//NB_COMMAND
#define NB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
#define NB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
#define NB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
#define NB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
#define NB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
#define NB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
//NB_STATUS
#define NB_STATUS__CAP_LIST__SHIFT 0x4
#define NB_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
#define NB_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
#define NB_STATUS__CAP_LIST_MASK 0x0010L
#define NB_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
#define NB_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
//NB_SUB_CLASS
#define NB_SUB_CLASS__SUB_CLASS_INF__SHIFT 0x0
#define NB_SUB_CLASS__SUB_CLASS_INF_MASK 0xFFL
//NB_BASE_CODE
#define NB_BASE_CODE__BASE_CLASS_CODE__SHIFT 0x0
#define NB_BASE_CODE__BASE_CLASS_CODE_MASK 0xFFL
//NB_CACHE_LINE
#define NB_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
#define NB_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
//NB_LATENCY
#define NB_LATENCY__LATENCY_TIMER__SHIFT 0x0
#define NB_LATENCY__LATENCY_TIMER_MASK 0xFFL
//NB_HEADER
#define NB_HEADER__HEADER_TYPE__SHIFT 0x0
#define NB_HEADER__DEVICE_TYPE__SHIFT 0x7
#define NB_HEADER__HEADER_TYPE_MASK 0x7FL
#define NB_HEADER__DEVICE_TYPE_MASK 0x80L
//NB_ADAPTER_ID
#define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
#define NB_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
#define NB_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
#define NB_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
//NB_CAPABILITIES_PTR
#define NB_CAPABILITIES_PTR__CAP_PTR__SHIFT 0x0
#define NB_CAPABILITIES_PTR__CAP_PTR_MASK 0x000000FFL
//NB_HEADER_W
#define NB_HEADER_W__DEVICE_TYPE__SHIFT 0x7
#define NB_HEADER_W__DEVICE_TYPE_MASK 0x00000080L
//NB_PCI_CTRL
#define NB_PCI_CTRL__PMEDis__SHIFT 0x4
#define NB_PCI_CTRL__SErrDis__SHIFT 0x5
#define NB_PCI_CTRL__MMIOEnable__SHIFT 0x17
#define NB_PCI_CTRL__HPDis__SHIFT 0x1a
#define NB_PCI_CTRL__PMEDis_MASK 0x00000010L
#define NB_PCI_CTRL__SErrDis_MASK 0x00000020L
#define NB_PCI_CTRL__MMIOEnable_MASK 0x00800000L
#define NB_PCI_CTRL__HPDis_MASK 0x04000000L
//NB_ADAPTER_ID_W
#define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
#define NB_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
#define NB_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
#define NB_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
//NBCFG_SCRATCH_0
#define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0__SHIFT 0x0
#define NBCFG_SCRATCH_0__NBCFG_SCRATCH_0_MASK 0xFFFFFFFFL
//NBCFG_SCRATCH_1
#define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1__SHIFT 0x0
#define NBCFG_SCRATCH_1__NBCFG_SCRATCH_1_MASK 0xFFFFFFFFL
//NBCFG_SCRATCH_2
#define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2__SHIFT 0x0
#define NBCFG_SCRATCH_2__NBCFG_SCRATCH_2_MASK 0xFFFFFFFFL
//NBCFG_SCRATCH_3
#define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3__SHIFT 0x0
#define NBCFG_SCRATCH_3__NBCFG_SCRATCH_3_MASK 0xFFFFFFFFL
//NBCFG_SCRATCH_4
#define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0
#define NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL
//NB_PCI_ARB
#define NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
#define NB_PCI_ARB__PMEMode__SHIFT 0x8
#define NB_PCI_ARB__PMETurnOff__SHIFT 0x9
#define NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa
#define NB_PCI_ARB__PMETarget__SHIFT 0x10
#define NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
#define NB_PCI_ARB__PMEMode_MASK 0x00000100LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.