drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h- Extension
.h- Size
- 10145 bytes
- Lines
- 293
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef OSS_1_0_D_H
#define OSS_1_0_D_H
#define ixCLIENT0_BM 0x0220
#define ixCLIENT0_CD0 0x0210
#define ixCLIENT0_CD1 0x0214
#define ixCLIENT0_CD2 0x0218
#define ixCLIENT0_CD3 0x021C
#define ixCLIENT0_CK0 0x0200
#define ixCLIENT0_CK1 0x0204
#define ixCLIENT0_CK2 0x0208
#define ixCLIENT0_CK3 0x020C
#define ixCLIENT0_K0 0x01F0
#define ixCLIENT0_K1 0x01F4
#define ixCLIENT0_K2 0x01F8
#define ixCLIENT0_K3 0x01FC
#define ixCLIENT0_OFFSET 0x0224
#define ixCLIENT0_OFFSET_HI 0x0290
#define ixCLIENT0_STATUS 0x0228
#define ixCLIENT1_BM 0x025C
#define ixCLIENT1_CD0 0x024C
#define ixCLIENT1_CD1 0x0250
#define ixCLIENT1_CD2 0x0254
#define ixCLIENT1_CD3 0x0258
#define ixCLIENT1_CK0 0x023C
#define ixCLIENT1_CK1 0x0240
#define ixCLIENT1_CK2 0x0244
#define ixCLIENT1_CK3 0x0248
#define ixCLIENT1_K0 0x022C
#define ixCLIENT1_K1 0x0230
#define ixCLIENT1_K2 0x0234
#define ixCLIENT1_K3 0x0238
#define ixCLIENT1_OFFSET 0x0260
#define ixCLIENT1_OFFSET_HI 0x0294
#define ixCLIENT1_PORT_STATUS 0x0264
#define ixCLIENT2_BM 0x01E4
#define ixCLIENT2_CD0 0x01D4
#define ixCLIENT2_CD1 0x01D8
#define ixCLIENT2_CD2 0x01DC
#define ixCLIENT2_CD3 0x01E0
#define ixCLIENT2_CK0 0x01C4
#define ixCLIENT2_CK1 0x01C8
#define ixCLIENT2_CK2 0x01CC
#define ixCLIENT2_CK3 0x01D0
#define ixCLIENT2_K0 0x01B4
#define ixCLIENT2_K1 0x01B8
#define ixCLIENT2_K2 0x01BC
#define ixCLIENT2_K3 0x01C0
#define ixCLIENT2_OFFSET 0x01E8
#define ixCLIENT2_OFFSET_HI 0x0298
#define ixCLIENT2_STATUS 0x01EC
#define ixCLIENT3_BM 0x02D4
#define ixCLIENT3_CD0 0x02C4
#define ixCLIENT3_CD1 0x02C8
#define ixCLIENT3_CD2 0x02CC
#define ixCLIENT3_CD3 0x02D0
#define ixCLIENT3_CK0 0x02B4
#define ixCLIENT3_CK1 0x02B8
#define ixCLIENT3_CK2 0x02BC
#define ixCLIENT3_CK3 0x02C0
#define ixCLIENT3_K0 0x02A4
#define ixCLIENT3_K1 0x02A8
#define ixCLIENT3_K2 0x02AC
#define ixCLIENT3_K3 0x02B0
#define ixCLIENT3_OFFSET 0x02D8
#define ixCLIENT3_OFFSET_HI 0x02A0
#define ixCLIENT3_STATUS 0x02DC
#define ixDH_TEST 0x0000
#define ixEXP0 0x0034
#define ixEXP1 0x0038
#define ixEXP2 0x003C
#define ixEXP3 0x0040
#define ixEXP4 0x0044
#define ixEXP5 0x0048
#define ixEXP6 0x004C
#define ixEXP7 0x0050
#define ixHFS_SEED0 0x0278
#define ixHFS_SEED1 0x027C
#define ixHFS_SEED2 0x0280
#define ixHFS_SEED3 0x0284
#define ixKEFUSE0 0x0268
#define ixKEFUSE1 0x026C
#define ixKEFUSE2 0x0270
#define ixKEFUSE3 0x0274
#define ixKHFS0 0x0004
#define ixKHFS1 0x0008
#define ixKHFS2 0x000C
#define ixKHFS3 0x0010
#define ixKSESSION0 0x0014
#define ixKSESSION1 0x0018
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.