drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h- Extension
.h- Size
- 62368 bytes
- Lines
- 1121
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef OSS_1_0_SH_MASK_H
#define OSS_1_0_SH_MASK_H
#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
#define CLIENT0_BM__RESERVED_MASK 0xffffffffL
#define CLIENT0_BM__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT0_K0__RESERVED_MASK 0xffffffffL
#define CLIENT0_K0__RESERVED__SHIFT 0x00000000
#define CLIENT0_K1__RESERVED_MASK 0xffffffffL
#define CLIENT0_K1__RESERVED__SHIFT 0x00000000
#define CLIENT0_K2__RESERVED_MASK 0xffffffffL
#define CLIENT0_K2__RESERVED__SHIFT 0x00000000
#define CLIENT0_K3__RESERVED_MASK 0xffffffffL
#define CLIENT0_K3__RESERVED__SHIFT 0x00000000
#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000
#define CLIENT1_BM__RESERVED_MASK 0xffffffffL
#define CLIENT1_BM__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT1_K0__RESERVED_MASK 0xffffffffL
#define CLIENT1_K0__RESERVED__SHIFT 0x00000000
#define CLIENT1_K1__RESERVED_MASK 0xffffffffL
#define CLIENT1_K1__RESERVED__SHIFT 0x00000000
#define CLIENT1_K2__RESERVED_MASK 0xffffffffL
#define CLIENT1_K2__RESERVED__SHIFT 0x00000000
#define CLIENT1_K3__RESERVED_MASK 0xffffffffL
#define CLIENT1_K3__RESERVED__SHIFT 0x00000000
#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000
#define CLIENT2_BM__RESERVED_MASK 0xffffffffL
#define CLIENT2_BM__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK1__RESERVED_MASK 0xffffffffLAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.