drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h- Extension
.h- Size
- 54193 bytes
- Lines
- 643
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef OSS_2_0_D_H
#define OSS_2_0_D_H
#define mmIH_VMID_0_LUT 0xf50
#define mmIH_VMID_1_LUT 0xf51
#define mmIH_VMID_2_LUT 0xf52
#define mmIH_VMID_3_LUT 0xf53
#define mmIH_VMID_4_LUT 0xf54
#define mmIH_VMID_5_LUT 0xf55
#define mmIH_VMID_6_LUT 0xf56
#define mmIH_VMID_7_LUT 0xf57
#define mmIH_VMID_8_LUT 0xf58
#define mmIH_VMID_9_LUT 0xf59
#define mmIH_VMID_10_LUT 0xf5a
#define mmIH_VMID_11_LUT 0xf5b
#define mmIH_VMID_12_LUT 0xf5c
#define mmIH_VMID_13_LUT 0xf5d
#define mmIH_VMID_14_LUT 0xf5e
#define mmIH_VMID_15_LUT 0xf5f
#define mmIH_RB_CNTL 0xf80
#define mmIH_RB_BASE 0xf81
#define mmIH_RB_RPTR 0xf82
#define mmIH_RB_WPTR 0xf83
#define mmIH_RB_WPTR_ADDR_HI 0xf84
#define mmIH_RB_WPTR_ADDR_LO 0xf85
#define mmIH_CNTL 0xf86
#define mmIH_LEVEL_STATUS 0xf87
#define mmIH_STATUS 0xf88
#define mmIH_PERFMON_CNTL 0xf89
#define mmIH_PERFCOUNTER0_RESULT 0xf8a
#define mmIH_PERFCOUNTER1_RESULT 0xf8b
#define mmIH_ADVFAULT_CNTL 0xf8c
#define mmSEM_MCIF_CONFIG 0xf90
#define mmSDMA_CONFIG 0xf91
#define mmSDMA1_CONFIG 0xf92
#define mmUVD_CONFIG 0xf93
#define mmVCE_CONFIG 0xf94
#define mmACP_CONFIG 0xf95
#define mmCPG_CONFIG 0xf96
#define mmCPC1_CONFIG 0xf97
#define mmCPC2_CONFIG 0xf98
#define mmSEM_STATUS 0xf99
#define mmSEM_EDC_CONFIG 0xf9a
#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
#define mmSEM_MAILBOX 0xf9c
#define mmSEM_MAILBOX_CONTROL 0xf9d
#define mmSEM_CHICKEN_BITS 0xf9e
#define mmSRBM_CNTL 0x390
#define mmSRBM_GFX_CNTL 0x391
#define mmSRBM_STATUS2 0x393
#define mmSRBM_STATUS 0x394
#define mmSRBM_CAM_INDEX 0x396
#define mmSRBM_CAM_DATA 0x397
#define mmSRBM_SOFT_RESET 0x398
#define mmSRBM_DEBUG_CNTL 0x399
#define mmSRBM_DEBUG_DATA 0x39a
#define mmSRBM_CHIP_REVISION 0x39b
#define mmCC_SYS_RB_REDUNDANCY 0x39f
#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
#define mmSRBM_MC_CLKEN_CNTL 0x3b3
#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
#define mmSRBM_DEBUG 0x3a4
#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
#define mmSRBM_READ_ERROR 0x3a6
#define mmSRBM_INT_CNTL 0x3a8
#define mmSRBM_INT_STATUS 0x3a9
#define mmSRBM_INT_ACK 0x3aa
#define mmSRBM_PERFMON_CNTL 0x700
#define mmSRBM_PERFCOUNTER0_SELECT 0x701
#define mmSRBM_PERFCOUNTER1_SELECT 0x702
#define mmSRBM_PERFCOUNTER0_LO 0x703
#define mmSRBM_PERFCOUNTER0_HI 0x704
#define mmSRBM_PERFCOUNTER1_LO 0x705
#define mmSRBM_PERFCOUNTER1_HI 0x706
#define mmCC_DRM_ID_STRAPS 0x1559
#define mmCGTT_DRM_CLK_CTRL0 0x1579
#define ixDH_TEST 0x0
#define ixKHFS0 0x4
#define ixKHFS1 0x8
#define ixKHFS2 0xc
#define ixKHFS3 0x10
#define ixKSESSION0 0x14
#define ixKSESSION1 0x18
#define ixKSESSION2 0x1c
#define ixKSESSION3 0x20Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.