drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h- Extension
.h- Size
- 39594 bytes
- Lines
- 472
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef OSS_2_4_D_H
#define OSS_2_4_D_H
#define mmIH_VMID_0_LUT 0xe00
#define mmIH_VMID_1_LUT 0xe01
#define mmIH_VMID_2_LUT 0xe02
#define mmIH_VMID_3_LUT 0xe03
#define mmIH_VMID_4_LUT 0xe04
#define mmIH_VMID_5_LUT 0xe05
#define mmIH_VMID_6_LUT 0xe06
#define mmIH_VMID_7_LUT 0xe07
#define mmIH_VMID_8_LUT 0xe08
#define mmIH_VMID_9_LUT 0xe09
#define mmIH_VMID_10_LUT 0xe0a
#define mmIH_VMID_11_LUT 0xe0b
#define mmIH_VMID_12_LUT 0xe0c
#define mmIH_VMID_13_LUT 0xe0d
#define mmIH_VMID_14_LUT 0xe0e
#define mmIH_VMID_15_LUT 0xe0f
#define mmIH_RB_CNTL 0xe30
#define mmIH_RB_BASE 0xe31
#define mmIH_RB_RPTR 0xe32
#define mmIH_RB_WPTR 0xe33
#define mmIH_RB_WPTR_ADDR_HI 0xe34
#define mmIH_RB_WPTR_ADDR_LO 0xe35
#define mmIH_CNTL 0xe36
#define mmIH_LEVEL_STATUS 0xe37
#define mmIH_STATUS 0xe38
#define mmIH_PERFMON_CNTL 0xe39
#define mmIH_PERFCOUNTER0_RESULT 0xe3a
#define mmIH_PERFCOUNTER1_RESULT 0xe3b
#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
#define mmIH_VERSION 0xe42
#define mmSEM_MCIF_CONFIG 0xf90
#define mmSDMA_CONFIG 0xf91
#define mmSDMA1_CONFIG 0xf92
#define mmUVD_CONFIG 0xf93
#define mmVCE_CONFIG 0xf94
#define mmACP_CONFIG 0xf95
#define mmCPG_CONFIG 0xf96
#define mmCPC1_CONFIG 0xf97
#define mmCPC2_CONFIG 0xf98
#define mmSEM_STATUS 0xf99
#define mmSEM_EDC_CONFIG 0xf9a
#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
#define mmSEM_MAILBOX 0xf9c
#define mmSEM_MAILBOX_CONTROL 0xf9d
#define mmSEM_CHICKEN_BITS 0xf9e
#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
#define mmSRBM_CNTL 0x390
#define mmSRBM_GFX_CNTL 0x391
#define mmSRBM_READ_CNTL 0x392
#define mmSRBM_STATUS2 0x393
#define mmSRBM_STATUS 0x394
#define mmSRBM_STATUS3 0x395
#define mmSRBM_SOFT_RESET 0x398
#define mmSRBM_DEBUG_CNTL 0x399
#define mmSRBM_DEBUG_DATA 0x39a
#define mmSRBM_CHIP_REVISION 0x39b
#define mmCC_SYS_RB_REDUNDANCY 0x39f
#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
#define mmSRBM_MC_CLKEN_CNTL 0x3b3
#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
#define mmSRBM_ISP_CLKEN_CNTL 0x3b9
#define mmSRBM_DEBUG 0x3a4
#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
#define mmSRBM_READ_ERROR 0x3a6
#define mmSRBM_READ_ERROR2 0x3ae
#define mmSRBM_INT_CNTL 0x3a8
#define mmSRBM_INT_STATUS 0x3a9
#define mmSRBM_INT_ACK 0x3aa
#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
#define mmSRBM_DSM_TRIG_CNTL0 0x3af
#define mmSRBM_DSM_TRIG_CNTL1 0x3b0
#define mmSRBM_DSM_TRIG_MASK0 0x3b1
#define mmSRBM_DSM_TRIG_MASK1 0x3b2
#define mmSRBM_PERFMON_CNTL 0x7c00
#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.