drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
Extension
.h
Size
79198 bytes
Lines
1465
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef OSS_3_0_1_ENUM_H
#define OSS_3_0_1_ENUM_H

typedef enum IH_CLIENT_ID {
	DC_IH_SRC_ID_START                               = 0x1,
	DC_IH_SRC_ID_END                                 = 0x1f,
	VGA_IH_SRC_ID_START                              = 0x20,
	VGA_IH_SRC_ID_END                                = 0x27,
	CAP_IH_SRC_ID_START                              = 0x28,
	CAP_IH_SRC_ID_END                                = 0x2f,
	VIP_IH_SRC_ID_START                              = 0x30,
	VIP_IH_SRC_ID_END                                = 0x3f,
	ROM_IH_SRC_ID_START                              = 0x40,
	ROM_IH_SRC_ID_END                                = 0x5d,
	BIF_IH_SRC_ID_START                              = 0x5e,
	SAM_IH_SRC_ID_START                              = 0x5f,
	SRBM_IH_SRC_ID_START                             = 0x60,
	SRBM_IH_SRC_ID_END                               = 0x67,
	UVD_IH_SRC_ID_START                              = 0x72,
	UVD_IH_SRC_ID_END                                = 0x85,
	VMC_IH_SRC_ID_START                              = 0x86,
	VMC_IH_SRC_ID_END                                = 0x8f,
	RLC_IH_SRC_ID_START                              = 0x90,
	RLC_IH_SRC_ID_END                                = 0xf3,
	PDMA_IH_SRC_ID_START                             = 0xf4,
	PDMA_IH_SRC_ID_END                               = 0xf7,
	CG_IH_SRC_ID_START                               = 0xf8,
	CG_IH_SRC_ID_END                                 = 0xff,
} IH_CLIENT_ID;
typedef enum IH_PERF_SEL {
	IH_PERF_SEL_CYCLE                                = 0x0,
	IH_PERF_SEL_IDLE                                 = 0x1,
	IH_PERF_SEL_INPUT_IDLE                           = 0x2,
	IH_PERF_SEL_CLIENT0_IH_STALL                     = 0x3,
	IH_PERF_SEL_CLIENT1_IH_STALL                     = 0x4,
	IH_PERF_SEL_CLIENT2_IH_STALL                     = 0x5,
	IH_PERF_SEL_CLIENT3_IH_STALL                     = 0x6,
	IH_PERF_SEL_CLIENT4_IH_STALL                     = 0x7,
	IH_PERF_SEL_CLIENT5_IH_STALL                     = 0x8,
	IH_PERF_SEL_CLIENT6_IH_STALL                     = 0x9,
	IH_PERF_SEL_CLIENT7_IH_STALL                     = 0xa,
	IH_PERF_SEL_RB_IDLE                              = 0xb,
	IH_PERF_SEL_RB_FULL                              = 0xc,
	IH_PERF_SEL_RB_OVERFLOW                          = 0xd,
	IH_PERF_SEL_RB_WPTR_WRITEBACK                    = 0xe,
	IH_PERF_SEL_RB_WPTR_WRAP                         = 0xf,
	IH_PERF_SEL_RB_RPTR_WRAP                         = 0x10,
	IH_PERF_SEL_MC_WR_IDLE                           = 0x11,
	IH_PERF_SEL_MC_WR_COUNT                          = 0x12,
	IH_PERF_SEL_MC_WR_STALL                          = 0x13,
	IH_PERF_SEL_MC_WR_CLEAN_PENDING                  = 0x14,
	IH_PERF_SEL_MC_WR_CLEAN_STALL                    = 0x15,
	IH_PERF_SEL_BIF_RISING                           = 0x16,
	IH_PERF_SEL_BIF_FALLING                          = 0x17,
	IH_PERF_SEL_CLIENT8_IH_STALL                     = 0x18,
	IH_PERF_SEL_CLIENT9_IH_STALL                     = 0x19,
	IH_PERF_SEL_CLIENT10_IH_STALL                    = 0x1a,
	IH_PERF_SEL_CLIENT11_IH_STALL                    = 0x1b,
	IH_PERF_SEL_CLIENT12_IH_STALL                    = 0x1c,
	IH_PERF_SEL_CLIENT13_IH_STALL                    = 0x1d,
	IH_PERF_SEL_CLIENT14_IH_STALL                    = 0x1e,
	IH_PERF_SEL_CLIENT15_IH_STALL                    = 0x1f,
	IH_PERF_SEL_CLIENT16_IH_STALL                    = 0x20,
	IH_PERF_SEL_CLIENT17_IH_STALL                    = 0x21,
	IH_PERF_SEL_CLIENT18_IH_STALL                    = 0x22,
	IH_PERF_SEL_CLIENT19_IH_STALL                    = 0x23,
	IH_PERF_SEL_CLIENT20_IH_STALL                    = 0x24,
	IH_PERF_SEL_CLIENT21_IH_STALL                    = 0x25,
	IH_PERF_SEL_CLIENT22_IH_STALL                    = 0x26,
	IH_PERF_SEL_CLIENT23_IH_STALL                    = 0x27,
} IH_PERF_SEL;
typedef enum SEM_PERF_SEL {
	SEM_PERF_SEL_CYCLE                               = 0x0,
	SEM_PERF_SEL_IDLE                                = 0x1,
	SEM_PERF_SEL_SDMA0_REQ_SIGNAL                    = 0x2,
	SEM_PERF_SEL_SDMA1_REQ_SIGNAL                    = 0x3,
	SEM_PERF_SEL_UVD_REQ_SIGNAL                      = 0x4,
	SEM_PERF_SEL_VCE0_REQ_SIGNAL                     = 0x5,
	SEM_PERF_SEL_ACP_REQ_SIGNAL                      = 0x6,
	SEM_PERF_SEL_ISP_REQ_SIGNAL                      = 0x7,
	SEM_PERF_SEL_VCE1_REQ_SIGNAL                     = 0x8,
	SEM_PERF_SEL_VP8_REQ_SIGNAL                      = 0x9,
	SEM_PERF_SEL_CPG_E0_REQ_SIGNAL                   = 0xa,
	SEM_PERF_SEL_CPG_E1_REQ_SIGNAL                   = 0xb,
	SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL             = 0xc,
	SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL             = 0xd,
	SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL             = 0xe,
	SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL             = 0xf,
	SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL             = 0x10,
	SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL             = 0x11,

Annotation

Implementation Notes