drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

Extension

.h

Size

190365 bytes

Lines

3559

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef OSS_3_0_1_SH_MASK_H
#define OSS_3_0_1_SH_MASK_H

#define IH_VMID_0_LUT__PASID_MASK 0xffff
#define IH_VMID_0_LUT__PASID__SHIFT 0x0
#define IH_VMID_1_LUT__PASID_MASK 0xffff
#define IH_VMID_1_LUT__PASID__SHIFT 0x0
#define IH_VMID_2_LUT__PASID_MASK 0xffff
#define IH_VMID_2_LUT__PASID__SHIFT 0x0
#define IH_VMID_3_LUT__PASID_MASK 0xffff
#define IH_VMID_3_LUT__PASID__SHIFT 0x0
#define IH_VMID_4_LUT__PASID_MASK 0xffff
#define IH_VMID_4_LUT__PASID__SHIFT 0x0
#define IH_VMID_5_LUT__PASID_MASK 0xffff
#define IH_VMID_5_LUT__PASID__SHIFT 0x0
#define IH_VMID_6_LUT__PASID_MASK 0xffff
#define IH_VMID_6_LUT__PASID__SHIFT 0x0
#define IH_VMID_7_LUT__PASID_MASK 0xffff
#define IH_VMID_7_LUT__PASID__SHIFT 0x0
#define IH_VMID_8_LUT__PASID_MASK 0xffff
#define IH_VMID_8_LUT__PASID__SHIFT 0x0
#define IH_VMID_9_LUT__PASID_MASK 0xffff
#define IH_VMID_9_LUT__PASID__SHIFT 0x0
#define IH_VMID_10_LUT__PASID_MASK 0xffff
#define IH_VMID_10_LUT__PASID__SHIFT 0x0
#define IH_VMID_11_LUT__PASID_MASK 0xffff
#define IH_VMID_11_LUT__PASID__SHIFT 0x0
#define IH_VMID_12_LUT__PASID_MASK 0xffff
#define IH_VMID_12_LUT__PASID__SHIFT 0x0
#define IH_VMID_13_LUT__PASID_MASK 0xffff
#define IH_VMID_13_LUT__PASID__SHIFT 0x0
#define IH_VMID_14_LUT__PASID_MASK 0xffff
#define IH_VMID_14_LUT__PASID__SHIFT 0x0
#define IH_VMID_15_LUT__PASID_MASK 0xffff
#define IH_VMID_15_LUT__PASID__SHIFT 0x0
#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
#define IH_RB_BASE__ADDR_MASK 0xffffffff
#define IH_RB_BASE__ADDR__SHIFT 0x0
#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
#define IH_RB_RPTR__OFFSET__SHIFT 0x2
#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
#define IH_RB_WPTR__OFFSET__SHIFT 0x2
#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
#define IH_CNTL__ENABLE_INTR_MASK 0x1
#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
#define IH_CNTL__MC_SWAP_MASK 0x6
#define IH_CNTL__MC_SWAP__SHIFT 0x1
#define IH_CNTL__RPTR_REARM_MASK 0x10
#define IH_CNTL__RPTR_REARM__SHIFT 0x4
#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
#define IH_CNTL__MC_VMID_MASK 0x1e000000
#define IH_CNTL__MC_VMID__SHIFT 0x19
#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.