drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_4_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_4_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_4_2_offset.h- Extension
.h- Size
- 26454 bytes
- Lines
- 264
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _osssys_4_4_2_OFFSET_HEADER
#define _osssys_4_4_2_OFFSET_HEADER
// addressBlock: aid_osssys_osssysdec
// base address: 0x4280
#define regIH_VMID_0_LUT 0x0000
#define regIH_VMID_0_LUT_BASE_IDX 0
#define regIH_VMID_1_LUT 0x0001
#define regIH_VMID_1_LUT_BASE_IDX 0
#define regIH_VMID_2_LUT 0x0002
#define regIH_VMID_2_LUT_BASE_IDX 0
#define regIH_VMID_3_LUT 0x0003
#define regIH_VMID_3_LUT_BASE_IDX 0
#define regIH_VMID_4_LUT 0x0004
#define regIH_VMID_4_LUT_BASE_IDX 0
#define regIH_VMID_5_LUT 0x0005
#define regIH_VMID_5_LUT_BASE_IDX 0
#define regIH_VMID_6_LUT 0x0006
#define regIH_VMID_6_LUT_BASE_IDX 0
#define regIH_VMID_7_LUT 0x0007
#define regIH_VMID_7_LUT_BASE_IDX 0
#define regIH_VMID_8_LUT 0x0008
#define regIH_VMID_8_LUT_BASE_IDX 0
#define regIH_VMID_9_LUT 0x0009
#define regIH_VMID_9_LUT_BASE_IDX 0
#define regIH_VMID_10_LUT 0x000a
#define regIH_VMID_10_LUT_BASE_IDX 0
#define regIH_VMID_11_LUT 0x000b
#define regIH_VMID_11_LUT_BASE_IDX 0
#define regIH_VMID_12_LUT 0x000c
#define regIH_VMID_12_LUT_BASE_IDX 0
#define regIH_VMID_13_LUT 0x000d
#define regIH_VMID_13_LUT_BASE_IDX 0
#define regIH_VMID_14_LUT 0x000e
#define regIH_VMID_14_LUT_BASE_IDX 0
#define regIH_VMID_15_LUT 0x000f
#define regIH_VMID_15_LUT_BASE_IDX 0
#define regIH_VMID_0_LUT_MM 0x0010
#define regIH_VMID_0_LUT_MM_BASE_IDX 0
#define regIH_VMID_1_LUT_MM 0x0011
#define regIH_VMID_1_LUT_MM_BASE_IDX 0
#define regIH_VMID_2_LUT_MM 0x0012
#define regIH_VMID_2_LUT_MM_BASE_IDX 0
#define regIH_VMID_3_LUT_MM 0x0013
#define regIH_VMID_3_LUT_MM_BASE_IDX 0
#define regIH_VMID_4_LUT_MM 0x0014
#define regIH_VMID_4_LUT_MM_BASE_IDX 0
#define regIH_VMID_5_LUT_MM 0x0015
#define regIH_VMID_5_LUT_MM_BASE_IDX 0
#define regIH_VMID_6_LUT_MM 0x0016
#define regIH_VMID_6_LUT_MM_BASE_IDX 0
#define regIH_VMID_7_LUT_MM 0x0017
#define regIH_VMID_7_LUT_MM_BASE_IDX 0
#define regIH_VMID_8_LUT_MM 0x0018
#define regIH_VMID_8_LUT_MM_BASE_IDX 0
#define regIH_VMID_9_LUT_MM 0x0019
#define regIH_VMID_9_LUT_MM_BASE_IDX 0
#define regIH_VMID_10_LUT_MM 0x001a
#define regIH_VMID_10_LUT_MM_BASE_IDX 0
#define regIH_VMID_11_LUT_MM 0x001b
#define regIH_VMID_11_LUT_MM_BASE_IDX 0
#define regIH_VMID_12_LUT_MM 0x001c
#define regIH_VMID_12_LUT_MM_BASE_IDX 0
#define regIH_VMID_13_LUT_MM 0x001d
#define regIH_VMID_13_LUT_MM_BASE_IDX 0
#define regIH_VMID_14_LUT_MM 0x001e
#define regIH_VMID_14_LUT_MM_BASE_IDX 0
#define regIH_VMID_15_LUT_MM 0x001f
#define regIH_VMID_15_LUT_MM_BASE_IDX 0
#define regIH_COOKIE_0 0x0020
#define regIH_COOKIE_0_BASE_IDX 0
#define regIH_COOKIE_1 0x0021
#define regIH_COOKIE_1_BASE_IDX 0
#define regIH_COOKIE_2 0x0022
#define regIH_COOKIE_2_BASE_IDX 0
#define regIH_COOKIE_3 0x0023
#define regIH_COOKIE_3_BASE_IDX 0
#define regIH_COOKIE_4 0x0024
#define regIH_COOKIE_4_BASE_IDX 0
#define regIH_COOKIE_5 0x0025
#define regIH_COOKIE_5_BASE_IDX 0
#define regIH_COOKIE_6 0x0026
#define regIH_COOKIE_6_BASE_IDX 0
#define regIH_COOKIE_7 0x0027
#define regIH_COOKIE_7_BASE_IDX 0
#define regIH_REGISTER_LAST_PART0 0x003f
#define regIH_REGISTER_LAST_PART0_BASE_IDX 0
#define regIH_RB_CNTL 0x0080Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.