drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_0_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_0_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_0_0_sh_mask.h- Extension
.h- Size
- 107240 bytes
- Lines
- 1030
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _osssys_7_0_0_SH_MASK_HEADER
#define _osssys_7_0_0_SH_MASK_HEADER
// addressBlock: osssys_osssysdec
//IH_VMID_0_LUT
#define IH_VMID_0_LUT__PASID__SHIFT 0x0
#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_1_LUT
#define IH_VMID_1_LUT__PASID__SHIFT 0x0
#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_2_LUT
#define IH_VMID_2_LUT__PASID__SHIFT 0x0
#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_3_LUT
#define IH_VMID_3_LUT__PASID__SHIFT 0x0
#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_4_LUT
#define IH_VMID_4_LUT__PASID__SHIFT 0x0
#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_5_LUT
#define IH_VMID_5_LUT__PASID__SHIFT 0x0
#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_6_LUT
#define IH_VMID_6_LUT__PASID__SHIFT 0x0
#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_7_LUT
#define IH_VMID_7_LUT__PASID__SHIFT 0x0
#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_8_LUT
#define IH_VMID_8_LUT__PASID__SHIFT 0x0
#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_9_LUT
#define IH_VMID_9_LUT__PASID__SHIFT 0x0
#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_10_LUT
#define IH_VMID_10_LUT__PASID__SHIFT 0x0
#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_11_LUT
#define IH_VMID_11_LUT__PASID__SHIFT 0x0
#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_12_LUT
#define IH_VMID_12_LUT__PASID__SHIFT 0x0
#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_13_LUT
#define IH_VMID_13_LUT__PASID__SHIFT 0x0
#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_14_LUT
#define IH_VMID_14_LUT__PASID__SHIFT 0x0
#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_15_LUT
#define IH_VMID_15_LUT__PASID__SHIFT 0x0
#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_0_LUT_MM
#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_1_LUT_MM
#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_2_LUT_MM
#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_3_LUT_MM
#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_4_LUT_MM
#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_5_LUT_MM
#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_6_LUT_MM
#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_7_LUT_MM
#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_8_LUT_MM
#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_9_LUT_MM
#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_10_LUT_MM
#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_11_LUT_MM
#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_12_LUT_MMAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.