drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_offset.h- Extension
.h- Size
- 65567 bytes
- Lines
- 631
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _pcie_6_1_0_OFFSET_HEADER
#define _pcie_6_1_0_OFFSET_HEADER
// addressBlock: pcie_container_pcs0_pcie_lcu_pcie_pcs_prime_pcie_master_x1_xx16_pcs_prime_dir
// base address: 0x11a08000
#define regDXIO_HWDID 0x2270800
#define regDXIO_HWDID_BASE_IDX 0
#define regDXIO_LINKAGE_LANEGRP 0x2270802
#define regDXIO_LINKAGE_LANEGRP_BASE_IDX 0
#define regDXIO_LINKAGE_KPDMX 0x2270803
#define regDXIO_LINKAGE_KPDMX_BASE_IDX 0
#define regDXIO_LINKAGE_KPMX 0x2270804
#define regDXIO_LINKAGE_KPFIFO 0x2270805
#define regDXIO_LINKAGE_KPNP 0x2270806
#define regMAC_CAPABILITIES1 0x2270814
#define regMAC_CAPABILITIES1_BASE_IDX 0
#define regMAC_CAPABILITIES2 0x2270815
#define regMAC_CAPABILITIES2_BASE_IDX 0
// addressBlock: pcie_container_pcie0_pswuscfg0_cfgdecp
// base address: 0x1a300000
#define regCOMMAND 0x0001
#define regCOMMAND_BASE_IDX 1
#define regSTATUS 0x0001
#define regSTATUS_BASE_IDX 1
#define regLATENCY 0x0003
#define regLATENCY_BASE_IDX 1
#define regHEADER 0x0003
#define regHEADER_BASE_IDX 1
#define regPCIE_LANE_ERROR_STATUS 0x009e
#define regPCIE_LANE_ERROR_STATUS_BASE_IDX 1
#define regPCIE_LANE_0_EQUALIZATION_CNTL 0x009f
#define regPCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_1_EQUALIZATION_CNTL 0x009f
#define regPCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_2_EQUALIZATION_CNTL 0x00a0
#define regPCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_3_EQUALIZATION_CNTL 0x00a0
#define regPCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_4_EQUALIZATION_CNTL 0x00a1
#define regPCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_5_EQUALIZATION_CNTL 0x00a1
#define regPCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_6_EQUALIZATION_CNTL 0x00a2
#define regPCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_7_EQUALIZATION_CNTL 0x00a2
#define regPCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_8_EQUALIZATION_CNTL 0x00a3
#define regPCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_9_EQUALIZATION_CNTL 0x00a3
#define regPCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_10_EQUALIZATION_CNTL 0x00a4
#define regPCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_11_EQUALIZATION_CNTL 0x00a4
#define regPCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_12_EQUALIZATION_CNTL 0x00a5
#define regPCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_13_EQUALIZATION_CNTL 0x00a5
#define regPCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_14_EQUALIZATION_CNTL 0x00a6
#define regPCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LANE_15_EQUALIZATION_CNTL 0x00a6
#define regPCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 1
#define regPCIE_LTR_ENH_CAP_LIST 0x00c8
#define regPCIE_LTR_ENH_CAP_LIST_BASE_IDX 1
#define regPCIE_LTR_CAP 0x00c9
#define regPCIE_LTR_CAP_BASE_IDX 1
#define regPCIE_L1_PM_SUB_CAP_LIST 0x00dc
#define regPCIE_L1_PM_SUB_CAP_LIST_BASE_IDX 1
#define regPCIE_L1_PM_SUB_CAP 0x00dd
#define regPCIE_L1_PM_SUB_CAP_BASE_IDX 1
#define regPCIE_L1_PM_SUB_CNTL 0x00de
#define regPCIE_L1_PM_SUB_CNTL_BASE_IDX 1
#define regPCIE_L1_PM_SUB_CNTL2 0x00df
#define regPCIE_L1_PM_SUB_CNTL2_BASE_IDX 1
#define regPCIE_MARGINING_ENH_CAP_LIST 0x0110
#define regPCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 1
// addressBlock: pcie_container_pcie0_pswusp0_pciedir_p
// base address: 0x1a340000
#define regPCIEP_RESERVED 0x10000
#define regPCIEP_RESERVED_BASE_IDX 1
#define regPCIEP_SCRATCH 0x10001
#define regPCIEP_SCRATCH_BASE_IDX 1
#define regPCIEP_PORT_CNTL 0x10010
#define regPCIEP_PORT_CNTL_BASE_IDX 1
#define regPCIE_TX_REQUESTER_ID 0x10021Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.