drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h- Extension
.h- Size
- 470511 bytes
- Lines
- 4251
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _pcie_6_1_0_SH_MASK_HEADER
#define _pcie_6_1_0_SH_MASK_HEADER
// addressBlock: pcie_container_pcs0_pcie_lcu_pcie_pcs_prime_pcie_master_x1_xx16_pcs_prime_dir
//DXIO_HWDID
#define DXIO_HWDID__Hardware_Revision__SHIFT 0x0
#define DXIO_HWDID__Hardware_Minor_Version_Number__SHIFT 0x6
#define DXIO_HWDID__Hardware_Major_Version_Number__SHIFT 0xd
#define DXIO_HWDID__Hardware_Revision_MASK 0x0000003FL
#define DXIO_HWDID__Hardware_Minor_Version_Number_MASK 0x00001FC0L
#define DXIO_HWDID__Hardware_Major_Version_Number_MASK 0x000FE000L
//DXIO_LINKAGE_LANEGRP
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses__SHIFT 0x0
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size__SHIFT 0x2
#define DXIO_LINKAGE_LANEGRP__Index_Offset__SHIFT 0x6
#define DXIO_LINKAGE_LANEGRP__Presence__SHIFT 0x14
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses_MASK 0x00000001L
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size_MASK 0x0000003CL
#define DXIO_LINKAGE_LANEGRP__Index_Offset_MASK 0x000FFFC0L
#define DXIO_LINKAGE_LANEGRP__Presence_MASK 0x0FF00000L
//DXIO_LINKAGE_KPDMX
#define DXIO_LINKAGE_KPDMX__Overlay__SHIFT 0x1
#define DXIO_LINKAGE_KPDMX__Base_Offset__SHIFT 0x6
#define DXIO_LINKAGE_KPDMX__Presence__SHIFT 0x14
#define DXIO_LINKAGE_KPDMX__Overlay_MASK 0x00000002L
#define DXIO_LINKAGE_KPDMX__Base_Offset_MASK 0x000FFFC0L
#define DXIO_LINKAGE_KPDMX__Presence_MASK 0x0FF00000L
//DXIO_LINKAGE_KPMX
//DXIO_LINKAGE_KPFIFO
//DXIO_LINKAGE_KPNP
//MAC_CAPABILITIES1
#define MAC_CAPABILITIES1__Number_of_Lanes__SHIFT 0x0
#define MAC_CAPABILITIES1__Number_of_Engines__SHIFT 0x8
#define MAC_CAPABILITIES1__Number_of_Lanes_MASK 0x0000003FL
#define MAC_CAPABILITIES1__Number_of_Engines_MASK 0x00003F00L
//MAC_CAPABILITIES2
#define MAC_CAPABILITIES2__reserved__SHIFT 0x0
#define MAC_CAPABILITIES2__reserved_MASK 0x00000001L
// addressBlock: pcie_container_pcie0_pswuscfg0_cfgdecp
//COMMAND
#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
#define COMMAND__AD_STEPPING__SHIFT 0x7
#define COMMAND__SERR_EN__SHIFT 0x8
#define COMMAND__FAST_B2B_EN__SHIFT 0x9
#define COMMAND__INT_DIS__SHIFT 0xa
#define COMMAND__IO_ACCESS_EN_MASK 0x0001L
#define COMMAND__MEM_ACCESS_EN_MASK 0x0002L
#define COMMAND__BUS_MASTER_EN_MASK 0x0004L
#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
#define COMMAND__PAL_SNOOP_EN_MASK 0x0020L
#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
#define COMMAND__AD_STEPPING_MASK 0x0080L
#define COMMAND__SERR_EN_MASK 0x0100L
#define COMMAND__FAST_B2B_EN_MASK 0x0200L
#define COMMAND__INT_DIS_MASK 0x0400L
//STATUS
#define STATUS__IMMEDIATE_READINESS__SHIFT 0x0
#define STATUS__INT_STATUS__SHIFT 0x3
#define STATUS__CAP_LIST__SHIFT 0x4
#define STATUS__PCI_66_CAP__SHIFT 0x5
#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
#define STATUS__DEVSEL_TIMING__SHIFT 0x9
#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
#define STATUS__IMMEDIATE_READINESS_MASK 0x0001L
#define STATUS__INT_STATUS_MASK 0x0008L
#define STATUS__CAP_LIST_MASK 0x0010L
#define STATUS__PCI_66_CAP_MASK 0x0020L
#define STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
#define STATUS__DEVSEL_TIMING_MASK 0x0600L
#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.