drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h- Extension
.h- Size
- 336431 bytes
- Lines
- 3301
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _sdma_4_4_2_SH_MASK_HEADER
#define _sdma_4_4_2_SH_MASK_HEADER
// addressBlock: aid_sdma_insts_sdma0_sdmadec
//SDMA_UCODE_ADDR
#define SDMA_UCODE_ADDR__VALUE__SHIFT 0x0
#define SDMA_UCODE_ADDR__VALUE_MASK 0x00003FFFL
//SDMA_UCODE_DATA
#define SDMA_UCODE_DATA__VALUE__SHIFT 0x0
#define SDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
//SDMA_F32_CNTL
#define SDMA_F32_CNTL__HALT__SHIFT 0x0
#define SDMA_F32_CNTL__STEP__SHIFT 0x1
#define SDMA_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
#define SDMA_F32_CNTL__RESET__SHIFT 0x8
#define SDMA_F32_CNTL__CHECKSUM_CLR__SHIFT 0x9
#define SDMA_F32_CNTL__HALT_MASK 0x00000001L
#define SDMA_F32_CNTL__STEP_MASK 0x00000002L
#define SDMA_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL
#define SDMA_F32_CNTL__RESET_MASK 0x00000100L
#define SDMA_F32_CNTL__CHECKSUM_CLR_MASK 0x00000200L
//SDMA_MMHUB_CNTL
#define SDMA_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
#define SDMA_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
//SDMA_MMHUB_TRUSTLVL
#define SDMA_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
#define SDMA_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x4
#define SDMA_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x8
#define SDMA_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0xc
#define SDMA_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0x10
#define SDMA_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0x14
#define SDMA_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x18
#define SDMA_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x1c
#define SDMA_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x0000000FL
#define SDMA_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x000000F0L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x00000F00L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x0000F000L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x000F0000L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00F00000L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x0F000000L
#define SDMA_MMHUB_TRUSTLVL__SECFLAG7_MASK 0xF0000000L
//SDMA_VM_CNTL
#define SDMA_VM_CNTL__CMD__SHIFT 0x0
#define SDMA_VM_CNTL__CMD_MASK 0x0000000FL
//SDMA_VM_CTX_LO
#define SDMA_VM_CTX_LO__ADDR__SHIFT 0x2
#define SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
//SDMA_VM_CTX_HI
#define SDMA_VM_CTX_HI__ADDR__SHIFT 0x0
#define SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA_ACTIVE_FCN_ID
#define SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0
#define SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
#define SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x1f
#define SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
#define SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
#define SDMA_ACTIVE_FCN_ID__VF_MASK 0x80000000L
//SDMA_VM_CTX_CNTL
#define SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0
#define SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4
#define SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L
#define SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L
//SDMA_VIRT_RESET_REQ
#define SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0
#define SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f
#define SDMA_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
#define SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L
//SDMA_VF_ENABLE
#define SDMA_VF_ENABLE__VF_ENABLE__SHIFT 0x0
#define SDMA_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
//SDMA_CONTEXT_REG_TYPE0
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_CNTL__SHIFT 0x0
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE__SHIFT 0x1
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_BASE_HI__SHIFT 0x2
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR__SHIFT 0x3
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_HI__SHIFT 0x4
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR__SHIFT 0x5
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_HI__SHIFT 0x6
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL__SHIFT 0xa
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_RPTR__SHIFT 0xb
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_OFFSET__SHIFT 0xc
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_LO__SHIFT 0xd
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_BASE_HI__SHIFT 0xe
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_SIZE__SHIFT 0xf
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_SKIP_CNTL__SHIFT 0x10
#define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_CONTEXT_STATUS__SHIFT 0x11Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.