drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
Extension
.h
Size
22398 bytes
Lines
548
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _sdma0_4_0_OFFSET_HEADER
#define _sdma0_4_0_OFFSET_HEADER



// addressBlock: sdma0_sdma0dec
// base address:	0x4980
#define mmSDMA0_UCODE_ADDR	0x0000
#define mmSDMA0_UCODE_ADDR_BASE_IDX	0
#define mmSDMA0_UCODE_DATA	0x0001
#define mmSDMA0_UCODE_DATA_BASE_IDX	0
#define mmSDMA0_VM_CNTL	0x0004
#define mmSDMA0_VM_CNTL_BASE_IDX	0
#define mmSDMA0_VM_CTX_LO	0x0005
#define mmSDMA0_VM_CTX_LO_BASE_IDX	0
#define mmSDMA0_VM_CTX_HI	0x0006
#define mmSDMA0_VM_CTX_HI_BASE_IDX	0
#define mmSDMA0_ACTIVE_FCN_ID	0x0007
#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX	0
#define mmSDMA0_VM_CTX_CNTL	0x0008
#define mmSDMA0_VM_CTX_CNTL_BASE_IDX	0
#define mmSDMA0_VIRT_RESET_REQ	0x0009
#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX	0
#define mmSDMA0_VF_ENABLE	0x000a
#define mmSDMA0_VF_ENABLE_BASE_IDX	0
#define mmSDMA0_CONTEXT_REG_TYPE0	0x000b
#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX	0
#define mmSDMA0_CONTEXT_REG_TYPE1	0x000c
#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX	0
#define mmSDMA0_CONTEXT_REG_TYPE2	0x000d
#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX	0
#define mmSDMA0_CONTEXT_REG_TYPE3	0x000e
#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX	0
#define mmSDMA0_PUB_REG_TYPE0	0x000f
#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX	0
#define mmSDMA0_PUB_REG_TYPE1	0x0010
#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX	0
#define mmSDMA0_PUB_REG_TYPE2	0x0011
#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX	0
#define mmSDMA0_PUB_REG_TYPE3	0x0012
#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX	0
#define mmSDMA0_MMHUB_CNTL	0x0013
#define mmSDMA0_MMHUB_CNTL_BASE_IDX	0
#define mmSDMA0_CONTEXT_GROUP_BOUNDARY	0x0019
#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX	0
#define mmSDMA0_POWER_CNTL	0x001a
#define mmSDMA0_POWER_CNTL_BASE_IDX	0
#define mmSDMA0_CLK_CTRL	0x001b
#define mmSDMA0_CLK_CTRL_BASE_IDX	0
#define mmSDMA0_CNTL	0x001c
#define mmSDMA0_CNTL_BASE_IDX	0
#define mmSDMA0_CHICKEN_BITS	0x001d
#define mmSDMA0_CHICKEN_BITS_BASE_IDX	0
#define mmSDMA0_GB_ADDR_CONFIG	0x001e
#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX	0
#define mmSDMA0_GB_ADDR_CONFIG_READ	0x001f
#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX	0
#define mmSDMA0_RB_RPTR_FETCH_HI	0x0020
#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX	0
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL	0x0021
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX	0
#define mmSDMA0_RB_RPTR_FETCH	0x0022
#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX	0
#define mmSDMA0_IB_OFFSET_FETCH	0x0023
#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX	0
#define mmSDMA0_PROGRAM	0x0024
#define mmSDMA0_PROGRAM_BASE_IDX	0
#define mmSDMA0_STATUS_REG	0x0025
#define mmSDMA0_STATUS_REG_BASE_IDX	0
#define mmSDMA0_STATUS1_REG	0x0026
#define mmSDMA0_STATUS1_REG_BASE_IDX	0
#define mmSDMA0_RD_BURST_CNTL	0x0027
#define mmSDMA0_RD_BURST_CNTL_BASE_IDX	0
#define mmSDMA0_HBM_PAGE_CONFIG	0x0028
#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX	0
#define mmSDMA0_UCODE_CHECKSUM	0x0029
#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX	0
#define mmSDMA0_F32_CNTL	0x002a
#define mmSDMA0_F32_CNTL_BASE_IDX	0
#define mmSDMA0_FREEZE	0x002b
#define mmSDMA0_FREEZE_BASE_IDX	0
#define mmSDMA0_PHASE0_QUANTUM	0x002c
#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX	0
#define mmSDMA0_PHASE1_QUANTUM	0x002d
#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX	0
#define mmSDMA_POWER_GATING	0x002e
#define mmSDMA_POWER_GATING_BASE_IDX	0
#define mmSDMA_PGFSM_CONFIG	0x002f
#define mmSDMA_PGFSM_CONFIG_BASE_IDX	0
#define mmSDMA_PGFSM_WRITE	0x0030

Annotation

Implementation Notes