drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
Extension
.h
Size
97390 bytes
Lines
1853
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _sdma0_4_0_SH_MASK_HEADER
#define _sdma0_4_0_SH_MASK_HEADER


// addressBlock: sdma0_sdma0dec
//SDMA0_UCODE_ADDR
#define SDMA0_UCODE_ADDR__VALUE__SHIFT	0x0
#define SDMA0_UCODE_ADDR__VALUE_MASK	0x00001FFFL
//SDMA0_UCODE_DATA
#define SDMA0_UCODE_DATA__VALUE__SHIFT	0x0
#define SDMA0_UCODE_DATA__VALUE_MASK	0xFFFFFFFFL
//SDMA0_VM_CNTL
#define SDMA0_VM_CNTL__CMD__SHIFT	0x0
#define SDMA0_VM_CNTL__CMD_MASK	0x0000000FL
//SDMA0_VM_CTX_LO
#define SDMA0_VM_CTX_LO__ADDR__SHIFT	0x2
#define SDMA0_VM_CTX_LO__ADDR_MASK	0xFFFFFFFCL
//SDMA0_VM_CTX_HI
#define SDMA0_VM_CTX_HI__ADDR__SHIFT	0x0
#define SDMA0_VM_CTX_HI__ADDR_MASK	0xFFFFFFFFL
//SDMA0_ACTIVE_FCN_ID
#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT	0x0
#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT	0x4
#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT	0x1f
#define SDMA0_ACTIVE_FCN_ID__VFID_MASK	0x0000000FL
#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK	0x7FFFFFF0L
#define SDMA0_ACTIVE_FCN_ID__VF_MASK	0x80000000L
//SDMA0_VM_CTX_CNTL
#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT	0x0
#define SDMA0_VM_CTX_CNTL__VMID__SHIFT	0x4
#define SDMA0_VM_CTX_CNTL__PRIV_MASK	0x00000001L
#define SDMA0_VM_CTX_CNTL__VMID_MASK	0x000000F0L
//SDMA0_VIRT_RESET_REQ
#define SDMA0_VIRT_RESET_REQ__VF__SHIFT	0x0
#define SDMA0_VIRT_RESET_REQ__PF__SHIFT	0x1f
#define SDMA0_VIRT_RESET_REQ__VF_MASK	0x0000FFFFL
#define SDMA0_VIRT_RESET_REQ__PF_MASK	0x80000000L
//SDMA0_VF_ENABLE
#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT	0x0
#define SDMA0_VF_ENABLE__VF_ENABLE_MASK	0x00000001L
//SDMA0_CONTEXT_REG_TYPE0
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT	0x0
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT	0x1
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT	0x2
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT	0x3
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT	0x4
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT	0x5
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT	0x6
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT	0x7
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT	0x8
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT	0x9
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT	0xa
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT	0xb
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT	0xc
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT	0xd
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT	0xe
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT	0xf
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT	0x10
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT	0x11
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT	0x12
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT	0x13
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK	0x00000001L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK	0x00000002L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK	0x00000004L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK	0x00000008L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK	0x00000010L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK	0x00000020L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK	0x00000040L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK	0x00000080L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK	0x00000100L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK	0x00000200L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK	0x00000400L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK	0x00000800L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK	0x00001000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK	0x00002000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK	0x00004000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK	0x00008000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK	0x00010000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK	0x00020000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK	0x00040000L
#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK	0x00080000L
//SDMA0_CONTEXT_REG_TYPE1
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT	0x8
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT	0x9
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT	0xa
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT	0xb
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT	0xc
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT	0xd
#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT	0xe
#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT	0xf

Annotation

Implementation Notes