drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h- Extension
.h- Size
- 110266 bytes
- Lines
- 1044
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _sdma5_4_2_2_OFFSET_HEADER
#define _sdma5_4_2_2_OFFSET_HEADER
// addressBlock: sdma5_sdma5dec
// base address: 0x7b000
#define mmSDMA5_UCODE_ADDR 0x0000
#define mmSDMA5_UCODE_ADDR_BASE_IDX 1
#define mmSDMA5_UCODE_DATA 0x0001
#define mmSDMA5_UCODE_DATA_BASE_IDX 1
#define mmSDMA5_VM_CNTL 0x0004
#define mmSDMA5_VM_CNTL_BASE_IDX 1
#define mmSDMA5_VM_CTX_LO 0x0005
#define mmSDMA5_VM_CTX_LO_BASE_IDX 1
#define mmSDMA5_VM_CTX_HI 0x0006
#define mmSDMA5_VM_CTX_HI_BASE_IDX 1
#define mmSDMA5_ACTIVE_FCN_ID 0x0007
#define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1
#define mmSDMA5_VM_CTX_CNTL 0x0008
#define mmSDMA5_VM_CTX_CNTL_BASE_IDX 1
#define mmSDMA5_VIRT_RESET_REQ 0x0009
#define mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1
#define mmSDMA5_VF_ENABLE 0x000a
#define mmSDMA5_VF_ENABLE_BASE_IDX 1
#define mmSDMA5_CONTEXT_REG_TYPE0 0x000b
#define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1
#define mmSDMA5_CONTEXT_REG_TYPE1 0x000c
#define mmSDMA5_CONTEXT_REG_TYPE1_BASE_IDX 1
#define mmSDMA5_CONTEXT_REG_TYPE2 0x000d
#define mmSDMA5_CONTEXT_REG_TYPE2_BASE_IDX 1
#define mmSDMA5_CONTEXT_REG_TYPE3 0x000e
#define mmSDMA5_CONTEXT_REG_TYPE3_BASE_IDX 1
#define mmSDMA5_PUB_REG_TYPE0 0x000f
#define mmSDMA5_PUB_REG_TYPE0_BASE_IDX 1
#define mmSDMA5_PUB_REG_TYPE1 0x0010
#define mmSDMA5_PUB_REG_TYPE1_BASE_IDX 1
#define mmSDMA5_PUB_REG_TYPE2 0x0011
#define mmSDMA5_PUB_REG_TYPE2_BASE_IDX 1
#define mmSDMA5_PUB_REG_TYPE3 0x0012
#define mmSDMA5_PUB_REG_TYPE3_BASE_IDX 1
#define mmSDMA5_MMHUB_CNTL 0x0013
#define mmSDMA5_MMHUB_CNTL_BASE_IDX 1
#define mmSDMA5_CONTEXT_GROUP_BOUNDARY 0x0019
#define mmSDMA5_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1
#define mmSDMA5_POWER_CNTL 0x001a
#define mmSDMA5_POWER_CNTL_BASE_IDX 1
#define mmSDMA5_CLK_CTRL 0x001b
#define mmSDMA5_CLK_CTRL_BASE_IDX 1
#define mmSDMA5_CNTL 0x001c
#define mmSDMA5_CNTL_BASE_IDX 1
#define mmSDMA5_CHICKEN_BITS 0x001d
#define mmSDMA5_CHICKEN_BITS_BASE_IDX 1
#define mmSDMA5_GB_ADDR_CONFIG 0x001e
#define mmSDMA5_GB_ADDR_CONFIG_BASE_IDX 1
#define mmSDMA5_GB_ADDR_CONFIG_READ 0x001f
#define mmSDMA5_GB_ADDR_CONFIG_READ_BASE_IDX 1
#define mmSDMA5_RB_RPTR_FETCH_HI 0x0020
#define mmSDMA5_RB_RPTR_FETCH_HI_BASE_IDX 1
#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1
#define mmSDMA5_RB_RPTR_FETCH 0x0022
#define mmSDMA5_RB_RPTR_FETCH_BASE_IDX 1
#define mmSDMA5_IB_OFFSET_FETCH 0x0023
#define mmSDMA5_IB_OFFSET_FETCH_BASE_IDX 1
#define mmSDMA5_PROGRAM 0x0024
#define mmSDMA5_PROGRAM_BASE_IDX 1
#define mmSDMA5_STATUS_REG 0x0025
#define mmSDMA5_STATUS_REG_BASE_IDX 1
#define mmSDMA5_STATUS1_REG 0x0026
#define mmSDMA5_STATUS1_REG_BASE_IDX 1
#define mmSDMA5_RD_BURST_CNTL 0x0027
#define mmSDMA5_RD_BURST_CNTL_BASE_IDX 1
#define mmSDMA5_HBM_PAGE_CONFIG 0x0028
#define mmSDMA5_HBM_PAGE_CONFIG_BASE_IDX 1
#define mmSDMA5_UCODE_CHECKSUM 0x0029
#define mmSDMA5_UCODE_CHECKSUM_BASE_IDX 1
#define mmSDMA5_F32_CNTL 0x002a
#define mmSDMA5_F32_CNTL_BASE_IDX 1
#define mmSDMA5_FREEZE 0x002b
#define mmSDMA5_FREEZE_BASE_IDX 1
#define mmSDMA5_PHASE0_QUANTUM 0x002c
#define mmSDMA5_PHASE0_QUANTUM_BASE_IDX 1
#define mmSDMA5_PHASE1_QUANTUM 0x002d
#define mmSDMA5_PHASE1_QUANTUM_BASE_IDX 1
#define mmSDMA5_EDC_CONFIG 0x0032
#define mmSDMA5_EDC_CONFIG_BASE_IDX 1
#define mmSDMA5_BA_THRESHOLD 0x0033
#define mmSDMA5_BA_THRESHOLD_BASE_IDX 1
#define mmSDMA5_ID 0x0034Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.