drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h- Extension
.h- Size
- 48101 bytes
- Lines
- 898
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef SMU_6_0_SH_MASK_H
#define SMU_6_0_SH_MASK_H
#define CG_AT__CG_R_MASK 0x0000FFFFL
#define CG_AT__CG_R__SHIFT 0x00000000
#define CG_AT__CG_L_MASK 0xFFFF0000L
#define CG_AT__CG_L__SHIFT 0x00000010
#define CG_BSP__BSP_MASK 0x0000FFFFL
#define CG_BSP__BSP__SHIFT 0x00000000
#define CG_BSP__BSU_MASK 0x000F0000L
#define CG_BSP__BSU__SHIFT 0x00000010
#define CG_CAC_CTRL__CAC_WINDOW_MASK 0x00FFFFFFL
#define CG_CAC_CTRL__CAC_WINDOW__SHIFT 0x00000000
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x00000002L
#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x00000001
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x00000004L
#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x00000002
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x00000008L
#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x00000003
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x00000100L
#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x00000008
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK 0x00000003L
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT 0x00000000
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK 0x0000000CL
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT 0x00000002
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x0003FFF0L
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x00000004
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x00700000
#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x00000014
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK 0x03000000L
#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT 0x00000018
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK 0x0C000000L
#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT 0x0000001A
#define CG_FFCT_0__UTC_0_MASK 0x000003FFL
#define CG_FFCT_0__UTC_0__SHIFT 0x00000000
#define CG_FFCT_0__DTC_0_MASK 0x000FFC00L
#define CG_FFCT_0__DTC_0__SHIFT 0x0000000A
#define CG_GIT__CG_GICST_MASK 0x0000FFFFL
#define CG_GIT__CG_GICST__SHIFT 0x00000000
#define CG_GIT__CG_GIPOT_MASK 0xFFFF0000L
#define CG_GIT__CG_GIPOT__SHIFT 0x00000010
#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x00000001L
#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK 0x00000002L
#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP__SHIFT 0x00000001
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x00000008L
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x00000003
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003F0L
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x007F00000
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x00000014
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x0000001FF
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x00800000
#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x00000017
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x04000000
#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x0000001A
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03FFFFFFL
#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000L
#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x0000001C
#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x00000002L
#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x00000001
#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x00000001L
#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x00000000
#define CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK 0x0000FFF0L
#define CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT 0x00000004
#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK 0x00000200L
#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT 0x00000000
#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK 0x03FFFFFFL
#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR__SHIFT 0x00000009
#define CG_SSP__SST_MASK 0x0000FFFFL
#define CG_SSP__SST__SHIFT 0x00000000
#define CG_SSP__SSTU_MASK 0x000F0000L
#define CG_SSP__SSTU__SHIFT 0x00000010
#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x00000007L
#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x00000000
#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x003FC000
#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0x0000000E
#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x00000009Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.