drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h

Extension

.h

Size

216936 bytes

Lines

3843

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef SMU_7_0_0_SH_MASK_H
#define SMU_7_0_0_SH_MASK_H

#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.