drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h- Extension
.h- Size
- 114919 bytes
- Lines
- 1317
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef SMU_7_0_1_D_H
#define SMU_7_0_1_D_H
#define mmGCK_SMC_IND_INDEX 0x80
#define mmGCK0_GCK_SMC_IND_INDEX 0x80
#define mmGCK1_GCK_SMC_IND_INDEX 0x82
#define mmGCK2_GCK_SMC_IND_INDEX 0x84
#define mmGCK3_GCK_SMC_IND_INDEX 0x86
#define mmGCK_SMC_IND_DATA 0x81
#define mmGCK0_GCK_SMC_IND_DATA 0x81
#define mmGCK1_GCK_SMC_IND_DATA 0x83
#define mmGCK2_GCK_SMC_IND_DATA 0x85
#define mmGCK3_GCK_SMC_IND_DATA 0x87
#define ixCG_DCLK_CNTL 0xc050009c
#define ixCG_DCLK_STATUS 0xc05000a0
#define ixCG_VCLK_CNTL 0xc05000a4
#define ixCG_VCLK_STATUS 0xc05000a8
#define ixCG_ECLK_CNTL 0xc05000ac
#define ixCG_ECLK_STATUS 0xc05000b0
#define ixCG_ACLK_CNTL 0xc05000dc
#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
#define ixCG_SPLL_FUNC_CNTL 0xc0500140
#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
#define ixCG_SPLL_STATUS 0xC050015C
#define ixSPLL_CNTL_MODE 0xc0500160
#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
#define ixMPLL_BYPASSCLK_SEL 0xc050019c
#define ixCG_CLKPIN_CNTL 0xc05001a0
#define ixCG_CLKPIN_CNTL_2 0xc05001a4
#define ixCG_CLKPIN_CNTL_DC 0xc0500204
#define ixTHM_CLK_CNTL 0xc05001a8
#define ixMISC_CLK_CTRL 0xc05001ac
#define ixGCK_PLL_TEST_CNTL 0xc05001c0
#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
#define mmSMC_IND_INDEX 0x80
#define mmSMC0_SMC_IND_INDEX 0x80
#define mmSMC1_SMC_IND_INDEX 0x82
#define mmSMC2_SMC_IND_INDEX 0x84
#define mmSMC3_SMC_IND_INDEX 0x86
#define mmSMC_IND_DATA 0x81
#define mmSMC0_SMC_IND_DATA 0x81
#define mmSMC1_SMC_IND_DATA 0x83
#define mmSMC2_SMC_IND_DATA 0x85
#define mmSMC3_SMC_IND_DATA 0x87
#define mmSMC_IND_INDEX_0 0x80
#define mmSMC_IND_DATA_0 0x81
#define mmSMC_IND_INDEX_1 0x82
#define mmSMC_IND_DATA_1 0x83
#define mmSMC_IND_INDEX_2 0x84
#define mmSMC_IND_DATA_2 0x85
#define mmSMC_IND_INDEX_3 0x86
#define mmSMC_IND_DATA_3 0x87
#define mmSMC_IND_INDEX_4 0x88
#define mmSMC_IND_DATA_4 0x89
#define mmSMC_IND_INDEX_5 0x8a
#define mmSMC_IND_DATA_5 0x8b
#define mmSMC_IND_INDEX_6 0x8c
#define mmSMC_IND_DATA_6 0x8d
#define mmSMC_IND_INDEX_7 0x8e
#define mmSMC_IND_DATA_7 0x8f
#define mmSMC_IND_ACCESS_CNTL 0x90
#define mmSMC_MESSAGE_0 0x94
#define mmSMC_RESP_0 0x95
#define mmSMC_MESSAGE_1 0x96
#define mmSMC_RESP_1 0x97
#define mmSMC_MESSAGE_2 0x98
#define mmSMC_RESP_2 0x99
#define mmSMC_MESSAGE_3 0x9a
#define mmSMC_RESP_3 0x9b
#define mmSMC_MESSAGE_4 0x9c
#define mmSMC_RESP_4 0x9d
#define mmSMC_MESSAGE_5 0x9e
#define mmSMC_RESP_5 0x9f
#define mmSMC_MESSAGE_6 0xa0
#define mmSMC_RESP_6 0xa1
#define mmSMC_MESSAGE_7 0xa2
#define mmSMC_RESP_7 0xa3
#define mmSMC_MSG_ARG_0 0xa4
#define mmSMC_MSG_ARG_1 0xa5
#define mmSMC_MSG_ARG_2 0xa6
#define mmSMC_MSG_ARG_3 0xa7
#define mmSMC_MSG_ARG_4 0xa8
#define mmSMC_MSG_ARG_5 0xa9Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.