drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
Extension
.h
Size
64301 bytes
Lines
1192
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef SMU_7_1_0_ENUM_H
#define SMU_7_1_0_ENUM_H

#define CG_SRBM_START_ADDR                        0x600
#define CG_SRBM_END_ADDR                          0x8ff
#define RCU_CCF_DWORDS0                           0x28
#define RCU_CCF_BITS0                             0x500
#define RCU_CCF_DWORDS1                           0x7f
#define RCU_CCF_BITS1                             0x1000
#define RCU_SAM_BYTES                             0x40
#define RCU_SAM_RTL_BYTES                         0x40
#define KEYS_CHAIN_ADR                            0x0
#define SAMU_KEY_SADR                             0xa0
#define SAMU_KEY_EADR                             0xdf
#define RCU_SMU_BYTES                             0x11
#define RCU_SMU_RTL_BYTES                         0x11
#define SMC_MSG_TEST                              0x1
#define SMC_MSG_PHY_LN_OFF                        0x2
#define SMC_MSG_PHY_LN_ON                         0x3
#define SMC_MSG_DDI_PHY_OFF                       0x4
#define SMC_MSG_DDI_PHY_ON                        0x5
#define SMC_MSG_CASCADE_PLL_OFF                   0x6
#define SMC_MSG_CASCADE_PLL_ON                    0x7
#define SMC_MSG_PWR_OFF_x16                       0x8
#define SMC_MSG_CONFIG_LCLK_DPM                   0x9
#define SMC_MSG_FLUSH_DATA_CACHE                  0xa
#define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
#define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
#define SMC_MSG_CONFIG_BAPM                       0xd
#define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
#define SMC_MSG_CONFIG_LPMx                       0xf
#define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
#define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
#define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
#define SMC_MSG_CONFIG_TDP_CNTL                   0x13
#define SMC_MSG_EN_PM_CNTL                        0x14
#define SMC_MSG_DIS_PM_CNTL                       0x15
#define SMC_MSG_CONFIG_NBDPM                      0x16
#define SMC_MSG_CONFIG_LOADLINE                   0x17
#define SMC_MSG_ADJUST_LOADLINE                   0x18
#define SMC_MSG_RESET                             0x20
#define SMC_MSG_VOLTAGE                           0x25
#define SMC_VERSION_MAJOR                         0x7
#define SMC_VERSION_MINOR                         0x0
#define SMC_HEADER_SIZE                           0x40
#define ROM_SIGNATURE                             0xaa55
typedef enum SurfaceEndian {
	ENDIAN_NONE                                      = 0x0,
	ENDIAN_8IN16                                     = 0x1,
	ENDIAN_8IN32                                     = 0x2,
	ENDIAN_8IN64                                     = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
	ARRAY_LINEAR_GENERAL                             = 0x0,
	ARRAY_LINEAR_ALIGNED                             = 0x1,
	ARRAY_1D_TILED_THIN1                             = 0x2,
	ARRAY_1D_TILED_THICK                             = 0x3,
	ARRAY_2D_TILED_THIN1                             = 0x4,
	ARRAY_PRT_TILED_THIN1                            = 0x5,
	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
	ARRAY_2D_TILED_THICK                             = 0x7,
	ARRAY_2D_TILED_XTHICK                            = 0x8,
	ARRAY_PRT_TILED_THICK                            = 0x9,
	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
	ARRAY_3D_TILED_THIN1                             = 0xc,
	ARRAY_3D_TILED_THICK                             = 0xd,
	ARRAY_3D_TILED_XTHICK                            = 0xe,
	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
} ArrayMode;
typedef enum PipeTiling {
	CONFIG_1_PIPE                                    = 0x0,
	CONFIG_2_PIPE                                    = 0x1,
	CONFIG_4_PIPE                                    = 0x2,
	CONFIG_8_PIPE                                    = 0x3,
} PipeTiling;
typedef enum BankTiling {
	CONFIG_4_BANK                                    = 0x0,
	CONFIG_8_BANK                                    = 0x1,
} BankTiling;
typedef enum GroupInterleave {
	CONFIG_256B_GROUP                                = 0x0,
	CONFIG_512B_GROUP                                = 0x1,
} GroupInterleave;
typedef enum RowTiling {
	CONFIG_1KB_ROW                                   = 0x0,
	CONFIG_2KB_ROW                                   = 0x1,
	CONFIG_4KB_ROW                                   = 0x2,
	CONFIG_8KB_ROW                                   = 0x3,
	CONFIG_1KB_ROW_OPT                               = 0x4,

Annotation

Implementation Notes