drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h

Extension

.h

Size

168645 bytes

Lines

2965

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef SMU_8_0_SH_MASK_H
#define SMU_8_0_SH_MASK_H

#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
#define THM_TCON_HTC__HTC_EN_MASK 0x1
#define THM_TCON_HTC__HTC_EN__SHIFT 0x0
#define THM_TCON_HTC__RSVD0_MASK 0x2
#define THM_TCON_HTC__RSVD0__SHIFT 0x1
#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4
#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2
#define THM_TCON_HTC__RSVD1_MASK 0x8
#define THM_TCON_HTC__RSVD1__SHIFT 0x3
#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10
#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4
#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20
#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5
#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40
#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6
#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80
#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7
#define THM_TCON_HTC__HTC_DIAG_MASK 0x100
#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8
#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200
#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9
#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400
#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa
#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800
#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb
#define THM_TCON_HTC__RSVD2_MASK 0xf000
#define THM_TCON_HTC__RSVD2__SHIFT 0xc
#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000
#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10
#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000
#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17
#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000
#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18
#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000
#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c
#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f
#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60
#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80
#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00
#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000
#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000
#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000
#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000
#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15
#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1
#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0
#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2
#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4
#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2
#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8
#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10
#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20
#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0
#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6
#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000
#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1
#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0
#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2
#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4
#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8
#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3
#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10
#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4
#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100
#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8
#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.