drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_offset.h- Extension
.h- Size
- 53441 bytes
- Lines
- 517
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _smuio_13_0_2_OFFSET_HEADER
#define _smuio_13_0_2_OFFSET_HEADER
// addressBlock: smuio_smuio_SmuSmuioDec
// base address: 0x5a000
#define regSMUSVI0_TEL_PLANE0 0x0004
#define regSMUSVI0_TEL_PLANE0_BASE_IDX 0
#define regSMUSVI0_PLANE0_CURRENTVID 0x0014
#define regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
#define regSMUIO_MCM_CONFIG 0x0024
#define regSMUIO_MCM_CONFIG_BASE_IDX 0
#define regCKSVII2C_IC_CON 0x0040
#define regCKSVII2C_IC_CON_BASE_IDX 0
#define regCKSVII2C_IC_TAR 0x0041
#define regCKSVII2C_IC_TAR_BASE_IDX 0
#define regCKSVII2C_IC_SAR 0x0042
#define regCKSVII2C_IC_SAR_BASE_IDX 0
#define regCKSVII2C_IC_HS_MADDR 0x0043
#define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0
#define regCKSVII2C_IC_DATA_CMD 0x0044
#define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0
#define regCKSVII2C_IC_SS_SCL_HCNT 0x0045
#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_SS_SCL_LCNT 0x0046
#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0
#define regCKSVII2C_IC_FS_SCL_HCNT 0x0047
#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_FS_SCL_LCNT 0x0048
#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0
#define regCKSVII2C_IC_HS_SCL_HCNT 0x0049
#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_HS_SCL_LCNT 0x004a
#define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0
#define regCKSVII2C_IC_INTR_STAT 0x004b
#define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0
#define regCKSVII2C_IC_INTR_MASK 0x004c
#define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0
#define regCKSVII2C_IC_RAW_INTR_STAT 0x004d
#define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0
#define regCKSVII2C_IC_RX_TL 0x004e
#define regCKSVII2C_IC_RX_TL_BASE_IDX 0
#define regCKSVII2C_IC_TX_TL 0x004f
#define regCKSVII2C_IC_TX_TL_BASE_IDX 0
#define regCKSVII2C_IC_CLR_INTR 0x0050
#define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0
#define regCKSVII2C_IC_CLR_RX_UNDER 0x0051
#define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0
#define regCKSVII2C_IC_CLR_RX_OVER 0x0052
#define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0
#define regCKSVII2C_IC_CLR_TX_OVER 0x0053
#define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0
#define regCKSVII2C_IC_CLR_RD_REQ 0x0054
#define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0
#define regCKSVII2C_IC_CLR_TX_ABRT 0x0055
#define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0
#define regCKSVII2C_IC_CLR_RX_DONE 0x0056
#define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0
#define regCKSVII2C_IC_CLR_ACTIVITY 0x0057
#define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0
#define regCKSVII2C_IC_CLR_STOP_DET 0x0058
#define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0
#define regCKSVII2C_IC_CLR_START_DET 0x0059
#define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0
#define regCKSVII2C_IC_CLR_GEN_CALL 0x005a
#define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0
#define regCKSVII2C_IC_ENABLE 0x005b
#define regCKSVII2C_IC_ENABLE_BASE_IDX 0
#define regCKSVII2C_IC_STATUS 0x005c
#define regCKSVII2C_IC_STATUS_BASE_IDX 0
#define regCKSVII2C_IC_TXFLR 0x005d
#define regCKSVII2C_IC_TXFLR_BASE_IDX 0
#define regCKSVII2C_IC_RXFLR 0x005e
#define regCKSVII2C_IC_RXFLR_BASE_IDX 0
#define regCKSVII2C_IC_SDA_HOLD 0x005f
#define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0
#define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060
#define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0
#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061
#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0
#define regCKSVII2C_IC_DMA_CR 0x0062
#define regCKSVII2C_IC_DMA_CR_BASE_IDX 0
#define regCKSVII2C_IC_DMA_TDLR 0x0063
#define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0
#define regCKSVII2C_IC_DMA_RDLR 0x0064
#define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0
#define regCKSVII2C_IC_SDA_SETUP 0x0065
#define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0
#define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.