drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_2_sh_mask.h- Extension
.h- Size
- 111582 bytes
- Lines
- 1164
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _smuio_13_0_2_SH_MASK_HEADER
#define _smuio_13_0_2_SH_MASK_HEADER
// addressBlock: smuio_smuio_SmuSmuioDec
//SMUSVI0_TEL_PLANE0
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
//SMUSVI0_PLANE0_CURRENTVID
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
//SMUIO_MCM_CONFIG
#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x1
#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x4
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x8
#define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0xa
#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000001L
#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000000EL
#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x000000F0L
#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00000300L
#define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00007C00L
//CKSVII2C_IC_CON
#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0
#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1
#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3
#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4
#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5
#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6
#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7
#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8
#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9
#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L
#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L
#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L
#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L
#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L
#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L
#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L
#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L
#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L
//CKSVII2C_IC_TAR
#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0
#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa
#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb
#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc
#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL
#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L
#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L
#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L
//CKSVII2C_IC_SAR
#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0
#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL
//CKSVII2C_IC_HS_MADDR
#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0
#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L
//CKSVII2C_IC_DATA_CMD
#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0
#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8
#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9
#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa
#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL
#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L
#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L
#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L
//CKSVII2C_IC_SS_SCL_HCNT
#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0
#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_SS_SCL_LCNT
#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0
#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_FS_SCL_HCNT
#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0
#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_FS_SCL_LCNT
#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0
#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_HS_SCL_HCNT
#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0
#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_HS_SCL_LCNT
#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0
#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL
//CKSVII2C_IC_INTR_STAT
#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0
#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1
#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2
#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.