drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h- Extension
.h- Size
- 51567 bytes
- Lines
- 513
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _smuio_15_0_8_OFFSET_HEADER
#define _smuio_15_0_8_OFFSET_HEADER
// addressBlock: smuio_smuio_tsc_SmuSmuioDec
// base address: 0x5a8a0
#define regPWROK_REFCLK_GAP_CYCLES 0x0028
#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
#define regGOLDEN_TSC_INCREMENT_UPPER 0x002b
#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
#define regGOLDEN_TSC_INCREMENT_LOWER 0x002c
#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
#define regGOLDEN_TSC_COUNT_UPPER 0x0030
#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
#define regGOLDEN_TSC_COUNT_LOWER 0x0031
#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0032
#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0033
#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
#define regSOC_GAP_PWROK 0x0034
#define regSOC_GAP_PWROK_BASE_IDX 1
// addressBlock: smuio_smuio_swtimer_SmuSmuioDec
// base address: 0x5aca8
#define regPWR_VIRT_RESET_REQ 0x012a
#define regPWR_VIRT_RESET_REQ_BASE_IDX 1
#define regPWR_DISP_TIMER_CONTROL 0x012b
#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1
#define regPWR_DISP_TIMER_DEBUG 0x012c
#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1
#define regPWR_DISP_TIMER2_CONTROL 0x012d
#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
#define regPWR_DISP_TIMER2_DEBUG 0x012e
#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1
#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x012f
#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
#define regPWR_IH_CONTROL 0x0130
#define regPWR_IH_CONTROL_BASE_IDX 1
// addressBlock: smuio_smuio_misc_SmuSmuioDec
// base address: 0x5a000
#define regSMUIO_MCM_CONFIG 0x0023
#define regSMUIO_MCM_CONFIG_BASE_IDX 0
#define regIP_DISCOVERY_VERSION 0x0000
#define regIP_DISCOVERY_VERSION_BASE_IDX 1
#define regSCRATCH_REGISTER0 0x01c9
#define regSCRATCH_REGISTER0_BASE_IDX 1
#define regSCRATCH_REGISTER1 0x01ca
#define regSCRATCH_REGISTER1_BASE_IDX 1
#define regSCRATCH_REGISTER2 0x01cb
#define regSCRATCH_REGISTER2_BASE_IDX 1
#define regSCRATCH_REGISTER3 0x01cc
#define regSCRATCH_REGISTER3_BASE_IDX 1
#define regSCRATCH_REGISTER4 0x01cd
#define regSCRATCH_REGISTER4_BASE_IDX 1
#define regSCRATCH_REGISTER5 0x01ce
#define regSCRATCH_REGISTER5_BASE_IDX 1
#define regSCRATCH_REGISTER6 0x01cf
#define regSCRATCH_REGISTER6_BASE_IDX 1
#define regSCRATCH_REGISTER7 0x01d0
#define regSCRATCH_REGISTER7_BASE_IDX 1
// addressBlock: smuio_smuio_i2c_SmuSmuioDec
// base address: 0x5a100
#define regCKSVII2C_IC_CON 0x0040
#define regCKSVII2C_IC_CON_BASE_IDX 0
#define regCKSVII2C_IC_TAR 0x0041
#define regCKSVII2C_IC_TAR_BASE_IDX 0
#define regCKSVII2C_IC_SAR 0x0042
#define regCKSVII2C_IC_SAR_BASE_IDX 0
#define regCKSVII2C_IC_HS_MADDR 0x0043
#define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0
#define regCKSVII2C_IC_DATA_CMD 0x0044
#define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0
#define regCKSVII2C_IC_SS_SCL_HCNT 0x0045
#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_SS_SCL_LCNT 0x0046
#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0
#define regCKSVII2C_IC_FS_SCL_HCNT 0x0047
#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_FS_SCL_LCNT 0x0048
#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0
#define regCKSVII2C_IC_HS_SCL_HCNT 0x0049
#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0
#define regCKSVII2C_IC_HS_SCL_LCNT 0x004aAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.