drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h- Extension
.h- Size
- 21603 bytes
- Lines
- 265
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _smuio_9_0_SH_MASK_HEADER
#define _smuio_9_0_SH_MASK_HEADER
// addressBlock: smuio_smuio_SmuSmuioDec
//ROM_CNTL
#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
//ROM_STATUS
#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
//CGTT_ROM_CLK_CTRL0
#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
//ROM_INDEX
#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
#define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
//ROM_DATA
#define ROM_DATA__ROM_DATA__SHIFT 0x0
#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
//ROM_START
#define ROM_START__ROM_START__SHIFT 0x0
#define ROM_START__ROM_START_MASK 0x00FFFFFFL
//ROM_SW_CNTL
#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
//ROM_SW_STATUS
#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
//ROM_SW_COMMAND
#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
//ROM_SW_DATA_1
#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_2
#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_3
#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_4
#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_5
#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_6
#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_7
#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_8
#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_9
#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_10
#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_11
#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_12
#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_13
#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_14
#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_15
#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
//ROM_SW_DATA_16Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.