drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h- Extension
.h- Size
- 25768 bytes
- Lines
- 258
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _thm_10_0_OFFSET_HEADER
#define _thm_10_0_OFFSET_HEADER
// addressBlock: thm_thm_SmuThmDec
// base address: 0x59800
#define mmTHM_TCON_CUR_TMP 0x0000
#define mmTHM_TCON_CUR_TMP_BASE_IDX 0
#define mmTHM_TCON_HTC 0x0001
#define mmTHM_TCON_HTC_BASE_IDX 0
#define mmTHM_TCON_THERM_TRIP 0x0002
#define mmTHM_TCON_THERM_TRIP_BASE_IDX 0
#define mmTHM_CTF_DELAY 0x0003
#define mmTHM_CTF_DELAY_BASE_IDX 0
#define mmTHM_GPIO_PROCHOT_CTRL 0x0004
#define mmTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0
#define mmTHM_THERMAL_INT_ENA 0x000a
#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
#define mmTHM_THERMAL_INT_CTRL 0x000b
#define mmTHM_THERMAL_INT_CTRL_BASE_IDX 0
#define mmTHM_THERMAL_INT_STATUS 0x000c
#define mmTHM_THERMAL_INT_STATUS_BASE_IDX 0
#define mmTHM_TMON0_RDIL0_DATA 0x000d
#define mmTHM_TMON0_RDIL0_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL1_DATA 0x000e
#define mmTHM_TMON0_RDIL1_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL2_DATA 0x000f
#define mmTHM_TMON0_RDIL2_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL3_DATA 0x0010
#define mmTHM_TMON0_RDIL3_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL4_DATA 0x0011
#define mmTHM_TMON0_RDIL4_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL5_DATA 0x0012
#define mmTHM_TMON0_RDIL5_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL6_DATA 0x0013
#define mmTHM_TMON0_RDIL6_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL7_DATA 0x0014
#define mmTHM_TMON0_RDIL7_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL8_DATA 0x0015
#define mmTHM_TMON0_RDIL8_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL9_DATA 0x0016
#define mmTHM_TMON0_RDIL9_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL10_DATA 0x0017
#define mmTHM_TMON0_RDIL10_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL11_DATA 0x0018
#define mmTHM_TMON0_RDIL11_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL12_DATA 0x0019
#define mmTHM_TMON0_RDIL12_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL13_DATA 0x001a
#define mmTHM_TMON0_RDIL13_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL14_DATA 0x001b
#define mmTHM_TMON0_RDIL14_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIL15_DATA 0x001c
#define mmTHM_TMON0_RDIL15_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR0_DATA 0x001d
#define mmTHM_TMON0_RDIR0_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR1_DATA 0x001e
#define mmTHM_TMON0_RDIR1_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR2_DATA 0x001f
#define mmTHM_TMON0_RDIR2_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR3_DATA 0x0020
#define mmTHM_TMON0_RDIR3_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR4_DATA 0x0021
#define mmTHM_TMON0_RDIR4_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR5_DATA 0x0022
#define mmTHM_TMON0_RDIR5_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR6_DATA 0x0023
#define mmTHM_TMON0_RDIR6_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR7_DATA 0x0024
#define mmTHM_TMON0_RDIR7_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR8_DATA 0x0025
#define mmTHM_TMON0_RDIR8_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR9_DATA 0x0026
#define mmTHM_TMON0_RDIR9_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR10_DATA 0x0027
#define mmTHM_TMON0_RDIR10_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR11_DATA 0x0028
#define mmTHM_TMON0_RDIR11_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR12_DATA 0x0029
#define mmTHM_TMON0_RDIR12_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR13_DATA 0x002a
#define mmTHM_TMON0_RDIR13_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR14_DATA 0x002b
#define mmTHM_TMON0_RDIR14_DATA_BASE_IDX 0
#define mmTHM_TMON0_RDIR15_DATA 0x002c
#define mmTHM_TMON0_RDIR15_DATA_BASE_IDX 0
#define mmTHM_TMON0_INT_DATA 0x002d
#define mmTHM_TMON0_INT_DATA_BASE_IDX 0
#define mmTHM_TMON0_CTRL 0x002eAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.