drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h

Extension

.h

Size

3576 bytes

Lines

59

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _thm_11_0_2_OFFSET_HEADER
#define _thm_11_0_2_OFFSET_HEADER


#define mmCG_MULT_THERMAL_STATUS                                                                       0x005f
#define mmCG_MULT_THERMAL_STATUS_BASE_IDX                                                              0

#define mmCG_FDO_CTRL0                                                                                 0x0067
#define mmCG_FDO_CTRL0_BASE_IDX                                                                        0

#define mmCG_FDO_CTRL1                                                                                 0x0068
#define mmCG_FDO_CTRL1_BASE_IDX                                                                        0

#define mmCG_FDO_CTRL2                                                                                 0x0069
#define mmCG_FDO_CTRL2_BASE_IDX                                                                        0

#define mmCG_TACH_CTRL                                                                                 0x006a
#define mmCG_TACH_CTRL_BASE_IDX                                                                        0

#define mmCG_TACH_STATUS                                                                               0x006b
#define mmCG_TACH_STATUS_BASE_IDX                                                                      0

#define mmTHM_THERMAL_INT_ENA                                                                          0x000a
#define mmTHM_THERMAL_INT_ENA_BASE_IDX                                                                 0
#define mmTHM_THERMAL_INT_CTRL                                                                         0x000b
#define mmTHM_THERMAL_INT_CTRL_BASE_IDX                                                                0

#define mmTHM_TCON_THERM_TRIP                                                                          0x0002
#define mmTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0

#define mmTHM_BACO_CNTL                                                                                0x0081
#define mmTHM_BACO_CNTL_BASE_IDX                                                                       0

#define mmCG_THERMAL_STATUS                                                                            0x006C
#define mmCG_THERMAL_STATUS_BASE_IDX                                                                   0

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.