drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_7_0_offset.h- Extension
.h- Size
- 272649 bytes
- Lines
- 2627
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _umc_6_7_0_OFFSET_HEADER
#define _umc_6_7_0_OFFSET_HEADER
// addressBlock: umc_w_phy_umc0_mca_ip_umc0_mca_map
// base address: 0x50f00
#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
#define regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
#define regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
#define regMCA_UMC_UMC0_MCUMC_SYNDT0_BASE_IDX 0
// addressBlock: umc_w_phy_umc0_umcch0_umcchdec
// base address: 0x50000
#define regUMCCH0_0_BaseAddrCS0 0x0000
#define regUMCCH0_0_BaseAddrCS0_BASE_IDX 0
#define regUMCCH0_0_AddrMaskCS01 0x0008
#define regUMCCH0_0_AddrMaskCS01_BASE_IDX 0
#define regUMCCH0_0_AddrSelCS01 0x0010
#define regUMCCH0_0_AddrSelCS01_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank0 0x0032
#define regUMCCH0_0_AddrHashBank0_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank1 0x0033
#define regUMCCH0_0_AddrHashBank1_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank2 0x0034
#define regUMCCH0_0_AddrHashBank2_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank3 0x0035
#define regUMCCH0_0_AddrHashBank3_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank4 0x0036
#define regUMCCH0_0_AddrHashBank4_BASE_IDX 0
#define regUMCCH0_0_AddrHashBank5 0x0037
#define regUMCCH0_0_AddrHashBank5_BASE_IDX 0
#define regUMCCH0_0_UMC_CONFIG 0x0040
#define regUMCCH0_0_UMC_CONFIG_BASE_IDX 0
#define regUMCCH0_0_EccCtrl 0x0053
#define regUMCCH0_0_EccCtrl_BASE_IDX 0
#define regUMCCH0_0_UmcLocalCap 0x0306
#define regUMCCH0_0_UmcLocalCap_BASE_IDX 0
#define regUMCCH0_0_EccErrCntSel 0x0328
#define regUMCCH0_0_EccErrCntSel_BASE_IDX 0
#define regUMCCH0_0_EccErrCnt 0x0329
#define regUMCCH0_0_EccErrCnt_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtlClk 0x0340
#define regUMCCH0_0_PerfMonCtlClk_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtrClk_Lo 0x0341
#define regUMCCH0_0_PerfMonCtrClk_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtrClk_Hi 0x0342
#define regUMCCH0_0_PerfMonCtrClk_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl1 0x0344
#define regUMCCH0_0_PerfMonCtl1_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr1_Lo 0x0345
#define regUMCCH0_0_PerfMonCtr1_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr1_Hi 0x0346
#define regUMCCH0_0_PerfMonCtr1_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl2 0x0347
#define regUMCCH0_0_PerfMonCtl2_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr2_Lo 0x0348
#define regUMCCH0_0_PerfMonCtr2_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr2_Hi 0x0349
#define regUMCCH0_0_PerfMonCtr2_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl3 0x034a
#define regUMCCH0_0_PerfMonCtl3_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr3_Lo 0x034b
#define regUMCCH0_0_PerfMonCtr3_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr3_Hi 0x034c
#define regUMCCH0_0_PerfMonCtr3_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl4 0x034d
#define regUMCCH0_0_PerfMonCtl4_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr4_Lo 0x034e
#define regUMCCH0_0_PerfMonCtr4_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr4_Hi 0x034f
#define regUMCCH0_0_PerfMonCtr4_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl5 0x0350
#define regUMCCH0_0_PerfMonCtl5_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr5_Lo 0x0351
#define regUMCCH0_0_PerfMonCtr5_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr5_Hi 0x0352
#define regUMCCH0_0_PerfMonCtr5_Hi_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtl6 0x0353
#define regUMCCH0_0_PerfMonCtl6_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr6_Lo 0x0354
#define regUMCCH0_0_PerfMonCtr6_Lo_BASE_IDX 0
#define regUMCCH0_0_PerfMonCtr6_Hi 0x0355Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.