drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

Extension

.h

Size

44910 bytes

Lines

794

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef UVD_4_0_SH_MASK_H
#define UVD_4_0_SH_MASK_H

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000
#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017
#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a
#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015
#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016
#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b
#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019
#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012
#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018
#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014
#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013
#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e
#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010
#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c
#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e
#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d
#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011
#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f
#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b
#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d
#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c
#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
#define UVD_CGC_GATE__IDCT__SHIFT 0x00000007
#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a
#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
#define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005
#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006
#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b
#define UVD_CGC_GATE__MPC_MASK 0x00000200L
#define UVD_CGC_GATE__MPC__SHIFT 0x00000009
#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
#define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002
#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008
#define UVD_CGC_GATE__RBC_MASK 0x00000010L
#define UVD_CGC_GATE__RBC__SHIFT 0x00000004
#define UVD_CGC_GATE__REGS_MASK 0x00000008L
#define UVD_CGC_GATE__REGS__SHIFT 0x00000003
#define UVD_CGC_GATE__SCPU_MASK 0x00080000L
#define UVD_CGC_GATE__SCPU__SHIFT 0x00000013
#define UVD_CGC_GATE__SYS_MASK 0x00000001L
#define UVD_CGC_GATE__SYS__SHIFT 0x00000000
#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d
#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
#define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f
#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e
#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010
#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.