drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h- Extension
.h- Size
- 40780 bytes
- Lines
- 801
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef UVD_4_2_SH_MASK_H
#define UVD_4_2_SH_MASK_H
#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
#define UVD_SEMA_CMD__MODE_MASK 0x40
#define UVD_SEMA_CMD__MODE__SHIFT 0x6
#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
#define UVD_SEMA_CMD__VMID_MASK 0xf00
#define UVD_SEMA_CMD__VMID__SHIFT 0x8
#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xffAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.