drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h- Extension
.h- Size
- 21365 bytes
- Lines
- 226
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _uvd_7_0_OFFSET_HEADER
#define _uvd_7_0_OFFSET_HEADER
// addressBlock: uvd0_uvd_pg_dec
// base address: 0x1fb00
#define mmUVD_POWER_STATUS 0x00c4
#define mmUVD_POWER_STATUS_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_CNTL 0x00cb
#define mmUVD_DPG_RBC_RB_CNTL_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_BASE_LOW 0x00cc
#define mmUVD_DPG_RBC_RB_BASE_LOW_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_BASE_HIGH 0x00cd
#define mmUVD_DPG_RBC_RB_BASE_HIGH_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_WPTR_CNTL 0x00ce
#define mmUVD_DPG_RBC_RB_WPTR_CNTL_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_RPTR 0x00cf
#define mmUVD_DPG_RBC_RB_RPTR_BASE_IDX 1
#define mmUVD_DPG_RBC_RB_WPTR 0x00d0
#define mmUVD_DPG_RBC_RB_WPTR_BASE_IDX 1
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6
#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7
#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
// addressBlock: uvd0_uvdnpdec
// base address: 0x20000
#define mmUVD_JPEG_ADDR_CONFIG 0x021f
#define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_GPCOM_VCPU_CMD 0x03c3
#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1
#define mmUVD_GPCOM_VCPU_DATA0 0x03c4
#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1
#define mmUVD_GPCOM_VCPU_DATA1 0x03c5
#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1
#define mmUVD_UDEC_ADDR_CONFIG 0x03d3
#define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4
#define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5
#define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_SUVD_CGC_GATE 0x03e4
#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1
#define mmUVD_SUVD_CGC_CTRL 0x03e6
#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed
#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1
#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1
#define mmUVD_POWER_STATUS_U 0x03fd
#define mmUVD_POWER_STATUS_U_BASE_IDX 1
#define mmUVD_NO_OP 0x03ff
#define mmUVD_NO_OP_BASE_IDX 1
#define mmUVD_GP_SCRATCH8 0x040a
#define mmUVD_GP_SCRATCH8_BASE_IDX 1
#define mmUVD_RB_BASE_LO2 0x0421
#define mmUVD_RB_BASE_LO2_BASE_IDX 1
#define mmUVD_RB_BASE_HI2 0x0422
#define mmUVD_RB_BASE_HI2_BASE_IDX 1
#define mmUVD_RB_SIZE2 0x0423
#define mmUVD_RB_SIZE2_BASE_IDX 1
#define mmUVD_RB_RPTR2 0x0424
#define mmUVD_RB_RPTR2_BASE_IDX 1
#define mmUVD_RB_WPTR2 0x0425
#define mmUVD_RB_WPTR2_BASE_IDX 1
#define mmUVD_RB_BASE_LO 0x0426
#define mmUVD_RB_BASE_LO_BASE_IDX 1
#define mmUVD_RB_BASE_HI 0x0427
#define mmUVD_RB_BASE_HI_BASE_IDX 1
#define mmUVD_RB_SIZE 0x0428
#define mmUVD_RB_SIZE_BASE_IDX 1
#define mmUVD_RB_RPTR 0x0429
#define mmUVD_RB_RPTR_BASE_IDX 1
#define mmUVD_RB_WPTR 0x042a
#define mmUVD_RB_WPTR_BASE_IDX 1
#define mmUVD_JRBC_RB_RPTR 0x0457
#define mmUVD_JRBC_RB_RPTR_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f
#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.