drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h- Extension
.h- Size
- 86517 bytes
- Lines
- 832
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _uvd_7_0_SH_MASK_HEADER
#define _uvd_7_0_SH_MASK_HEADER
// addressBlock: uvd0_uvd_pg_dec
//UVD_POWER_STATUS
#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x00000008L
#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x00000010L
#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x00000020L
#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0x000000C0L
#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x00000200L
#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x00000400L
//UVD_DPG_RBC_RB_CNTL
#define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
#define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
#define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
#define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
#define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
#define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
#define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
#define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
#define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
#define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
//UVD_DPG_RBC_RB_BASE_LOW
#define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW__SHIFT 0x0
#define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW_MASK 0xFFFFFFFFL
//UVD_DPG_RBC_RB_BASE_HIGH
#define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH__SHIFT 0x0
#define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH_MASK 0xFFFFFFFFL
//UVD_DPG_RBC_RB_WPTR_CNTL
#define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
#define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
//UVD_DPG_RBC_RB_RPTR
#define UVD_DPG_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
#define UVD_DPG_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
//UVD_DPG_RBC_RB_WPTR
#define UVD_DPG_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
#define UVD_DPG_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
//UVD_DPG_VCPU_CACHE_OFFSET0
#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
// addressBlock: uvd0_uvdnpdec
//UVD_JPEG_ADDR_CONFIG
#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
#define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
#define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.