drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h

Extension

.h

Size

2603 bytes

Lines

70

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef VCE_1_0_D_H
#define VCE_1_0_D_H

#define mmVCE_CLOCK_GATING_A 0x80BE
#define mmVCE_CLOCK_GATING_B 0x80BF
#define mmVCE_LMI_CACHE_CTRL 0x83BD
#define mmVCE_LMI_CTRL 0x83A6
#define mmVCE_LMI_CTRL2 0x839D
#define mmVCE_LMI_MISC_CTRL 0x83B5
#define mmVCE_LMI_STATUS 0x83A7
#define mmVCE_LMI_SWAP_CNTL 0x83AD
#define mmVCE_LMI_SWAP_CNTL1 0x83AE
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397
#define mmVCE_LMI_VM_CTRL 0x83A8
#define mmVCE_RB_ARB_CTRL 0x809F
#define mmVCE_RB_BASE_HI 0x8061
#define mmVCE_RB_BASE_HI2 0x805C
#define mmVCE_RB_BASE_LO 0x8060
#define mmVCE_RB_BASE_LO2 0x805B
#define mmVCE_RB_RPTR 0x8063
#define mmVCE_RB_RPTR2 0x805E
#define mmVCE_RB_SIZE 0x8062
#define mmVCE_RB_SIZE2 0x805D
#define mmVCE_RB_WPTR 0x8064
#define mmVCE_RB_WPTR2 0x805F
#define mmVCE_SOFT_RESET 0x8048
#define mmVCE_STATUS 0x8001
#define mmVCE_SYS_INT_ACK 0x8341
#define mmVCE_SYS_INT_EN 0x8340
#define mmVCE_SYS_INT_STATUS 0x8341
#define mmVCE_UENC_CLOCK_GATING 0x816F
#define mmVCE_UENC_DMA_DCLK_CTRL 0x8250
#define mmVCE_UENC_REG_CLOCK_GATING 0x8170
#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
#define mmVCE_VCPU_CACHE_OFFSET1 0x800B
#define mmVCE_VCPU_CACHE_OFFSET2 0x800D
#define mmVCE_VCPU_CACHE_SIZE0 0x800A
#define mmVCE_VCPU_CACHE_SIZE1 0x800C
#define mmVCE_VCPU_CACHE_SIZE2 0x800E
#define mmVCE_VCPU_CNTL 0x8005
#define mmVCE_VCPU_SCRATCH7 0x8037
#define mmVCE_FW_REG_STATUS 0x8384
#define mmVCE_LMI_FW_PERIODIC_CTRL 0x8388
#define mmVCE_LMI_FW_START_KEYSEL 0x8386


#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.