drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h
Extension: .h
Size: 5143 bytes
Lines: 74
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef VCE_3_0_D_H
#define VCE_3_0_D_H

#define mmVCE_STATUS                                                            0x8001
#define mmVCE_VCPU_CNTL                                                         0x8005
#define mmVCE_VCPU_CACHE_OFFSET0                                                0x8009
#define mmVCE_VCPU_CACHE_SIZE0                                                  0x800a
#define mmVCE_VCPU_CACHE_OFFSET1                                                0x800b
#define mmVCE_VCPU_CACHE_SIZE1                                                  0x800c
#define mmVCE_VCPU_CACHE_OFFSET2                                                0x800d
#define mmVCE_VCPU_CACHE_SIZE2                                                  0x800e
#define mmVCE_SOFT_RESET                                                        0x8048
#define mmVCE_RB_BASE_LO2                                                       0x805b
#define mmVCE_RB_BASE_HI2                                                       0x805c
#define mmVCE_RB_SIZE2                                                          0x805d
#define mmVCE_RB_RPTR2                                                          0x805e
#define mmVCE_RB_WPTR2                                                          0x805f
#define mmVCE_RB_BASE_LO                                                        0x8060
#define mmVCE_RB_BASE_HI                                                        0x8061
#define mmVCE_RB_SIZE                                                           0x8062
#define mmVCE_RB_RPTR                                                           0x8063
#define mmVCE_RB_WPTR                                                           0x8064
#define mmVCE_RB_ARB_CTRL                                                       0x809f
#define mmVCE_CLOCK_GATING_A                                                    0x80be
#define mmVCE_CLOCK_GATING_B                                                    0x80bf
#define mmVCE_RB_BASE_LO3                                                       0x80d4
#define mmVCE_RB_BASE_HI3                                                       0x80d5
#define mmVCE_RB_SIZE3                                                          0x80d6
#define mmVCE_RB_RPTR3                                                          0x80d7
#define mmVCE_RB_WPTR3                                                          0x80d8
#define mmVCE_UENC_DMA_DCLK_CTRL                                                0x8390
#define mmVCE_UENC_CLOCK_GATING                                                 0x81ef
#define mmVCE_UENC_REG_CLOCK_GATING                                             0x81f0
#define mmVCE_UENC_CLOCK_GATING_2                                               0x8210
#define mmVCE_SYS_INT_EN                                                        0x8540
#define mmVCE_SYS_INT_STATUS                                                    0x8541
#define mmVCE_SYS_INT_ACK                                                       0x8541
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR                                          0x8597
#define mmVCE_LMI_CTRL2                                                         0x859d
#define mmVCE_LMI_SWAP_CNTL3                                                    0x859e
#define mmVCE_LMI_CTRL                                                          0x85a6
#define mmVCE_LMI_STATUS                                                        0x85a7
#define mmVCE_LMI_VM_CTRL                                                       0x85a8
#define mmVCE_LMI_SWAP_CNTL                                                     0x85ad
#define mmVCE_LMI_SWAP_CNTL1                                                    0x85ae
#define mmVCE_LMI_SWAP_CNTL2                                                    0x85b3
#define mmVCE_LMI_MISC_CTRL                                                     0x85b5
#define mmVCE_LMI_CACHE_CTRL                                                    0x85bd

#endif /* VCE_3_0_D_H */

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.